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From iis-projects
Welcome to IIS-Projects
In this page you will find student and research projects at the Integrated Systems Laboratory of the ETH Zurich.
Institute Organization
The IIS Consists of 6 main research groups
- Analog and Mixed Signal Design
- Digital Circuits and Systems
- Energy Efficient Circuits and IoT Systems
- Nano-TCAD
- Integrated Information Processing
- Physical Characterization
Analog and Mixed Signal Design Group (Prof. Huang)
- Analog IC Design
- Biomedical System on Chips
- Wireless Communication Systems for the IoT
- High-Performance & V2X Cellular Communications
Digital Circuits and Systems Group (Prof. Benini)
- High Performance SoCs
- Acceleration and Transprecision
- Heterogeneous SoCs
- Event-Driven Computing
- Predictable Execution
- Low Power Embedded Systems and Wireless Sensors Networks
- Embedded Artificial Intelligence:Systems And Applications
- Students' International Competitions: F1(AMZ), Swissloop, Educational Rockets
- Wireless Communication Systems for the IoT
- Energy Efficient Autonomous UAVs
- Biomedical System on Chips
- Digital Medical Ultrasound Imaging
- Cryptographic Hardware
- Deep Learning Acceleration
- Human Intranet
- IBM Research
Energy Efficient Circuits and IoT Systems Group (Prof. Jang)
- Palm size chip NMR probe
- MmWave PLL: 100GHz PLL using reference oversampling scheme
- Energy Efficient Circuits for Wireless Neural Recording
- Design of key building blocks for miniaturized sensor systems
- Application Specific Frequency Synthesizers (Analog/Digital PLLs)
Nano-TCAD Group (Prof. Luisier)
- Electrical characterization and optimization of electrochemical random-access memory for analog computing
- Optical Weights for Photonic Neural Networks
- Ab-initio modeling of ballistic thermal transport
Integrated Information Processing Group (Prof. Studer)
- Beamspace processing for 5G mmWave massive MIMO on GPU
- FFT HDL Code Generator for Multi-Antenna mmWave Communication
- Deep Unfolding of Iterative Optimization Algorithms
- Low-Resolution 5G Beamforming Codebook Design
- Design-Space Exploration of Low-Resolution Matrix-Vector Multipliers
- Practical Reconfigurable Intelligent Surfaces (RIS)
- Cell-Free mmWave Massive MIMO Communication
- Self-Supervised User Positioning in Cell-Free Massive MIMO Systems
- Semi-Custom Digital VLSI for Processing-in-Memory
- Signal Acquisition and Clock Offset Compensation for High-Rate Pulse UWB PHYs
- Peak-to-average power Reduction
Physical Characterization Group (Dr.Ciappa)
- Characterization of the susceptibility to cosmic radiation of wide bandgap power devices by radioactive sources and at cryogenic temperatures
- Design of an on-field adaptable pulse-processing unit for semicondutor radiation detectors
- Design and Exploitation of a Test-Bench for Non-Destructive Characterization of the Susceptibility of Silicon Carbide (SiC) Power Devices to Cosmic Radiation
- Experimental Validation of Impact Ionization Models for TCAD Simulation by a Novel Characterization Technique
- Design and implementation of the front-end for a portable ionizing radiation detector
Collaborations with other groups/departments
Selected Projects in Progress
For a complete list, see Projects in Progress.
- Next Generation Synchronization Signals
- Low Latency Brain-Machine Interfaces
- ISA extensions in the Snitch Processor for Signal Processing (M)
- MemPool on HERO (1S)
- PULP in space - Fault Tolerant PULP System for Critical Space Applications
Selected Completed Projects
For a complete list, see Completed Projects.
- NVDLA meets PULP
- Hardware Accelerators for Lossless Quantized Deep Neural Networks
- Energy-Efficient Brain-Inspired Hyperdimensional Computing
- A Recurrent Neural Network Speech Recognition Chip
- Implementation of a Heterogeneous System for Image Processing on an FPGA (S)
Selected Research Projects
For a complete list, see Research Projects.
- NVDLA meets PULP
- Hardware Accelerators for Lossless Quantized Deep Neural Networks
- Energy-Efficient Brain-Inspired Hyperdimensional Computing
- A Recurrent Neural Network Speech Recognition Chip
- Implementation of a Heterogeneous System for Image Processing on an FPGA (S)
Links to Other IIS Webpages
- http://www.iis.ee.ethz.ch
- Integrated Systems Laboratory Main homepage
- http://www.nano-tcad.ethz.ch
- Nano-TCAD group homepage
- http://www.dz.ee.ethz.ch
- Microelectronics Design Center
- http://asic.ethz.ch/cg
- The IIS-ASIC Chip Gallery
- http://eda.ee.ethz.ch
- EDA Wiki (ETH Zurich internal access only!)
