User:Aottaviano
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Alessandro Ottaviano
My research interest involves the world of Integrated Circuits and Computer Architecture, especially VLSI FPGA/ASIC design and Real Time Predictable embedded systems.
My work leverages the interface between SW (Real Time Operative Systems - RTOS and C systems programming) and HW (HDL design, FPGA emulation, gate-level ASIC design) towards the implementation of General Purpose computing platforms on silicon.
Contact
- Office: ETZ J89
- E-Mail: aottaviano@iis.ee.ethz.ch
- Phone: +41 44 632 57 45
Projects
Available Projects
- FPGA mapping of RPC DRAM
- Resource Partitioning of RPC DRAM
- PULP Freertos with LLVM
- Fast Accelerator Context Switch for PULP
- Non-blocking Algorithms in Real-Time Operating Systems
Projects In Progress
Completed Projects
- Design and Implementation of a Fully-digital Platform-independent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B)
- Resource Partitioning of Caches
- Development of statistics and contention monitoring unit for PULP
- Peripheral Event Linking System for Real-time Capable Energy Efficient SoCs
- CLIC for the CVA6
- SCMI Support for Power Controller Subsystem
- Efficient Synchronization of Manycore Systems (M/1S)
- A Unified Compute Kernel Library for Snitch (1-2S)
- PULP’s CLIC extensions for fast interrupt handling
- Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S)
- Physical Implementation of Ara, PULP's Vector Machine (1-2S)
- An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
