Quest for the smallest Turing-complete core (2-3G)
From iis-projects
The printable version is no longer supported and may have rendering errors. Please update your browser bookmarks and please use the default browser print function instead.
Introduction
When teaching EDA-tools to students, it is hard to find well-suited example applications. Ad-hoc and synthetic examples, like a simple shift register, are not complex enough and frankly just boring whereas fully-developed IPs, like a processor core, consists of tens to hundreds of thousands gates. Even our smallest core so far, the Snitch core, consists of approximately 20’000 gates.
We are therefore seeking a Turing-complete core with the smallest number of gates possible. You are free to choose a suitable instruction set architecture (ISA) for the task.
Project Content
The project can be divided in the following sub tasks:
- Explore already existing (esoteric) ISAs to find a suitable candidate or define one of yourselves
- Design a core. Try to see if you can “synthesize” it to a gate-level netlist by hand
- Use an industry-grade hardware synthesizer to synthesize your core
- Evaluate and improve both the ISA and your core to shrink it in size
- Stretch goal: Create a simple assembler / compiler to execute code on your core
Prerequisites
- Interest in computer architecture
- Preferably: Experience with HDLs as taught in VLSI I
Composition
- 30% Exploration
- 30% Implementation
- 40% Evaluation
