...le:StreamingProc.png|thumb|400px|The streaming processor would act as a co-processor for the DMA in the PULP cluster.]]
...icient data transfers. In this work, we are going to design a streaming co-processor for the DMA with limited programmability.
2 KB (344 words) - 10:30, 5 November 2019
[[File:Ultra-low power processor design.jpg|thumb]]
...use a state of the art 28nm SOI process to evaluate the performance of the processor.
10 KB (1,669 words) - 19:01, 30 January 2014
...his project is to develop a simple vector processor which can be used as a processor in memory (PIM) element. During the thesis you are going to study ongoing r
: Interest in processor design
3 KB (443 words) - 13:10, 2 November 2015
...rophone into the digital domain and transfers the samples to a voice codec processor. The latter filters and compresses the data. This is done on a CPU/DSP dedi
In this project a hardwired voice codec processor for commonly used voice codecs in 2G/3G/4G voice communication shall be imp
1 KB (229 words) - 18:01, 29 March 2017
The goal of this project is to design a processor using existing components and port it to an FPGA-based prototyping platform
2 KB (347 words) - 17:58, 14 April 2016
...classes motor-imagery and often they are not implemented in a neuromorphic processor, and none of them are presenting a whole system from the data acquisition t
6 KB (815 words) - 20:02, 10 March 2024
...a dedicated processor architecture, the goal of this project is to build a processor for sigma point belief propagation. Application specific processors of this
...ng designs and start with back-end design. After the back-end, your signal processor ASIC will be fabricated in high-end 65nm CMOS technology.
2 KB (265 words) - 08:34, 20 January 2021
...is usually attached as a fixed-function-unit to a heterogeneous multicore processor.
The goal of this project is to build an ASIC design of the processor architecture. You will start by optimizing the existing VHDL and Matlab mod
1 KB (210 words) - 08:34, 20 January 2021
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0 bytes (0 words) - 19:24, 2 November 2020
...Additionally, it can support he ‘M’ and ‘F’ extension through a custom co-processor interface. However, currently, there is no support for domain-specific inst
...the OpenHW Group [<nowiki/>[[#ref-CV32E40P|7]]]. It is a 32-bit in-order processor with 4 pipeline stages. In contrast to Snitch, it features custom DSP instr
9 KB (1,311 words) - 00:08, 13 March 2021
...of this project are rather challenging as the VLSI architecture of a VLIW processor is by far more complex than that of a RISC architecture. We therefore recom
...Thesis]] [[Category:2016]] [[Category:ASIC]] [[Category:PULP]] [[Category:Processor]]
3 KB (377 words) - 10:25, 5 November 2019
...d system architecture will be developed around an Ultra low power parallel processor developed at IIS to show to be ideally suited to interface
4 KB (518 words) - 11:40, 2 February 2018
-
2 KB (302 words) - 12:09, 26 March 2015
<!-- Design of a Reconfigurable Vector Processor Cluster for Area Efficient Radar Processing (1M) -->
The aim of this project is to design a reconfigurable vector processor cluster for area-optimized, yet compute and energy-efficient, radar signal
5 KB (651 words) - 20:42, 22 November 2022
...ery effectively, providing better energy efficiency than a general purpose processor for applications that fit its execution model.
...ner, Luca Benini. Ara: A 1GHz+ Scalable and Energy-Efficient RISC-V Vector Processor with Multi-Precision Floating Point Support in 22nm FD-SOI. [https://doi.or
4 KB (627 words) - 14:42, 29 October 2020
#REDIRECT [[DMA Streaming Co-processor]]
40 bytes (4 words) - 18:10, 14 April 2016
#REDIRECT [[Baseband Processor Development for 4G IoT]]
55 bytes (7 words) - 14:46, 28 May 2015
#REDIRECT [[Digital Audio Processor for Cellular Applications]]
63 bytes (7 words) - 16:36, 3 August 2015
...is usually attached as a fixed-function-unit to a heterogeneous multicore processor.
The goal of this project is to build an ASIC design of the processor architecture. You will start by optimizing the existing VHDL and Matlab mod
1 KB (210 words) - 08:34, 20 January 2021
...a dedicated processor architecture, the goal of this project is to build a processor for sigma point belief propagation. Application specific processors of this
...ng designs and start with back-end design. After the back-end, your signal processor ASIC will be fabricated in high-end 65nm CMOS technology.
2 KB (265 words) - 08:34, 20 January 2021
...le:StreamingProc.png|thumb|400px|The streaming processor would act as a co-processor for the DMA in the PULP cluster.]]
...icient data transfers. In this work, we are going to design a streaming co-processor for the DMA with limited programmability.
2 KB (344 words) - 10:30, 5 November 2019
...rophone into the digital domain and transfers the samples to a voice codec processor. The latter filters and compresses the data. This is done on a CPU/DSP dedi
In this project a hardwired voice codec processor for commonly used voice codecs in 2G/3G/4G voice communication shall be imp
1 KB (229 words) - 18:01, 29 March 2017
...ated in the pipeline. In a multi-processor environment one private FPU per processor core is not the most energy efficient implementation because ''floating poi
...multiply-add FPU, implement it in System Verilog and plug it to the RISC-V processor.
2 KB (346 words) - 10:26, 5 November 2019
...ailable before the power outage, i.e., the supply voltage is dropping, the processor state can be saved only when a power outage is imminent and thus superfluou
Both scenarios require a mechanism to save a snapshot of the processor state in a non-volatile memory. This mechanism is commonly known as '''hibe
3 KB (390 words) - 11:59, 20 June 2016
...ated in the pipeline. In a multi-processor environment one private FPU per processor core is not the most energy efficient implementation because ''floating poi
...referred algorithm in hardware such that it can be integrated in the multi-processor platform.
3 KB (377 words) - 10:58, 21 February 2018
...cores. ETH is at the forefront of this race with its agile in-order vector processor Ara, fresh from an update from the unripe specifications RVV 0.5.
...enchmarks based on open-source vector ISA RVV 0.5, evaluate them on vector processor Ara, and try to achieve their best performance.
3 KB (470 words) - 11:34, 3 November 2023
...mplementation of the OpenRisc was completed as part of a [[Ultra-low power processor design | previous semester thesis]]. We are already using this core in our
...e, during this wake up it will store the incoming message and allowing the processor to access the incoming data and react to it.
4 KB (667 words) - 15:23, 23 December 2016
IBM recently contributed their A2O processor core to the open-source community. The A2O is a 2-way multithreaded out-of-
...nm technology node. It was created as an application-grade, Linux-capable processor to be integrated in large SoCs primarily targeting applications like artifi
3 KB (405 words) - 15:19, 9 July 2021
* Processor Design
578 bytes (56 words) - 18:59, 30 October 2020
An application-specific instruction-set processor (ASIP) tailored to
In addition to the "pseudo-processor-controlled approach", the
2 KB (326 words) - 12:26, 26 March 2015
...a energy-efficient general-purpose vector processor, and extend the vector processor to cope with the new challenges to run efficiently transformer models.
...ent has already experience in programming and developing on the Ara vector processor from his previous semester thesis.
4 KB (549 words) - 11:35, 3 November 2023
...le, “FUGAKU”, the most performant supercomputer in the world, is a vector processor!
What a time for a project on a vector processor! RISC-V has almost finished ratifying its open-source vector ISA RVV (a pro
5 KB (665 words) - 14:19, 18 October 2022
...his project is to develop a simple vector processor which can be used as a processor in memory (PIM) element. During the thesis you are going to study ongoing r
: Interest in processor design
3 KB (443 words) - 13:10, 2 November 2015
At the IIS we are working on an ultra low-power multi-processor
processing applications that can be included in the multi-processor
3 KB (407 words) - 10:57, 5 November 2019
...do not need to execute very quickly. Therefore, existing hardware within a processor can be leveraged for reliability.
In this project, the goal is to modify a simple embedded RISC-V processor, such as Ibex [1]. The Ibex core supports both the riscv32i and the riscv32
2 KB (259 words) - 11:55, 18 December 2023
