...le, “FUGAKU”, the most performant supercomputer in the world, is a vector processor!
What a time for a project on a vector processor! RISC-V has almost finished ratifying its open-source vector ISA RVV (a pro
4 KB (580 words) - 11:37, 3 November 2023
...m the ADC HW-FIFO to SW-FIFO at kernel-space and the real-time embedded co-processor ([http://beagleboard.org/pru PRU]) for post-processing of the data-stream.
*[http://www.ti.com/lit/ds/symlink/am3358.pdf AM335x Sitara Processor Datasheet]
3 KB (394 words) - 16:19, 27 February 2018
GrÆStl cryptographic co-processor. Bottom: Photo of the manufactured Chameleon chip, host-
...r to accelerate the computations of the cryptographic primitives. Both the processor and GrÆStl were ported onto a low-cost FPGA and finally a comparison betwe
3 KB (434 words) - 12:01, 26 March 2015
...le, “FUGAKU”, the most performant supercomputer in the world, is a vector processor!
What a time for a project on a vector processor! RISC-V has almost finished ratifying its open-source vector ISA RVV (a pro
4 KB (524 words) - 12:36, 29 January 2024
<!-- Design of a Reconfigurable Vector Processor Cluster for Area Efficient Radar Processing (1M) -->
The aim of this project is to design a reconfigurable vector processor cluster for area-optimized, yet compute and energy-efficient, radar signal
5 KB (651 words) - 20:42, 22 November 2022
...cessor. The decoding of the RLC blocks takes place on a PHY Digital Signal Processor (DSP) and an accelerator attached to it.
3 KB (397 words) - 14:12, 27 May 2015
[[File:Ultra-low power processor design.jpg|thumb]]
...use a state of the art 28nm SOI process to evaluate the performance of the processor.
10 KB (1,669 words) - 19:01, 30 January 2014
* Processor Design
931 bytes (108 words) - 10:30, 22 November 2021
...le, “FUGAKU”, the most performant supercomputer in the world, is a vector processor!
What a time for a project on a vector processor! RISC-V has almost finished ratifying its open-source vector ISA RVV (a pro
5 KB (769 words) - 11:38, 3 November 2023
...sensors and one or two algorithms will be implemented directly in the PULP processor. One of main challenging goal of the project is bring these algorithm in an
* programming the PULP processor for the specific application, otimize the code and carry out in-field testi
4 KB (631 words) - 11:39, 21 July 2017
...n are the most important requirements of such a system. For this purpose a processor which only supports the basic instructions is enough. A very simple 2-3stag
...Thesis]] [[Category:2016]] [[Category:ASIC]] [[Category:PULP]] [[Category:Processor]]
3 KB (384 words) - 17:24, 21 August 2019
...of this project are rather challenging as the VLSI architecture of a VLIW processor is by far more complex than that of a RISC architecture. We therefore recom
...Thesis]] [[Category:2016]] [[Category:ASIC]] [[Category:PULP]] [[Category:Processor]]
3 KB (377 words) - 10:25, 5 November 2019
...are, exploiting a dedicated Floating-Point Unit (FPU). This means that the processor uses a circuit that was specifically designed to compute FP operations. Thi
...FP operation with a specific function that uses only integer numbers. The processor executes this function on the FP input numbers, and, after many integer ins
4 KB (536 words) - 13:25, 12 August 2022
...and the BioWolf wearable ExG device, which has the PULP Mr. Wolf multicore processor on board. The project’s goal is to design a system capable of acquiring r
...0-mW 8-Channel Advanced Brain–Computer Interface Platform With a Nine-Core Processor and BLE Connectivity
3 KB (369 words) - 15:04, 20 July 2023
...sed measurements, neural stimulation etc.) as well as powerful, PULP-based processor cores. Applications are in the field of optogenetics stimulation, ExG recor
...he field of wireless communication. Our current platform with a multi-core processor system and a great RF transceiver allows us to research upcoming wireless t
3 KB (369 words) - 18:11, 1 March 2023
*[http://www.ti.com/lit/ds/symlink/am3358.pdf AM335x Sitara Processor Datasheet]
*[http://www.ti.com/lit/ug/spruh73n/spruh73n.pdf AM335x Sitara Processor TRM]
3 KB (351 words) - 16:19, 27 February 2018
At the IIS we are working on an ultra low-power multi-processor (PULP)
multi-processor shared-memory cluster.
3 KB (409 words) - 10:52, 27 March 2014
...thumb|800px|These two ''timing channel matrices'' of a Haswell class Intel processor show the conditional probability of observing an output symbol (vertical ax
...tigate how such ''hardware knobs'' can be added to the Ariane 64bit RISC-V processor and come up with a proof-of-concept implementation. Insights gained during
6 KB (915 words) - 18:16, 20 May 2020
...e to implement custom co-processors and ISA extensions for existing RISC-V processor cores. Just like Ibex [1], the work for this extension interface has been s
...ng unit (VPU), or the development of a new accelerator such as a string co-processor. The project can be done in the context of a single-core or multi-core syst
6 KB (835 words) - 12:52, 27 April 2021
...ract additional data. The idea is to use the very efficient GAP9 multicore processor and deploy multi-modal neural networks to perform feature extraction, predi
...l power and efficiency of the main SoC, the multicore ultra-low-power GAP9 processor. Together with this, a sensing node has been developed targeting the sensin
4 KB (579 words) - 14:14, 16 May 2024
