User contributions
From iis-projects
- 10:09, 19 August 2022 diff hist +593 PULP
- 10:01, 19 August 2022 diff hist +236 PULP →Related Chips
- 09:32, 16 August 2022 diff hist +124 Digital →Completed Projects
- 18:06, 17 November 2021 diff hist +1 User:Smazzola →Completed Projects
- 18:06, 17 November 2021 diff hist -1 User:Smazzola
- 18:05, 17 November 2021 diff hist +5 Augmenting Our IPs with AXI Stream Extensions (M/1-2S)
- 17:22, 18 October 2021 diff hist +34 Analog Compute-in-Memory Accelerator Interface and Integration
- 17:21, 18 October 2021 diff hist +49 Analog Compute-in-Memory Accelerator Interface and Integration
- 11:39, 4 August 2021 diff hist +144 PULP →65nm
- 14:03, 14 July 2021 diff hist +91 PULP →65nm
- 14:42, 30 June 2021 diff hist +374 PULP →65nm
- 16:55, 4 May 2021 diff hist +131 PULP →22nm
- 14:51, 8 April 2021 diff hist -2 PULP →Related Chips
- 14:50, 8 April 2021 diff hist +401 PULP →Related Chips
- 20:04, 27 January 2021 diff hist +1,535 N ASIC Design Projects Created page with "__NOTOC__ <center> <H1>Design your ASIC</H1> 800px|Do you want to design your own chip </center> ===How does it work=== You want to do your very own AS..."
- 20:00, 27 January 2021 diff hist +6 N File:Yourchip.jpg Dustin current
- 08:42, 20 January 2021 diff hist -17 Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RI5CY core current
- 08:41, 20 January 2021 diff hist +88 Digital
- 08:40, 20 January 2021 diff hist -23 Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core
- 08:38, 20 January 2021 diff hist -62 Extend the RI5CY core with priviledge extensions current
- 08:37, 20 January 2021 diff hist -39 Autoencoder Accelerator for On-Chip Semi-Supervised Learning current
- 08:36, 20 January 2021 diff hist -39 Convolution Neural Networks on our Ultra-Low Power Mult-Core Plattform PULP current
- 08:35, 20 January 2021 diff hist -23 Compressed Sensing for Wireless Biosignal Monitoring current
- 08:35, 20 January 2021 diff hist -22 Fast Wakeup From Deep Sleep State current
- 08:35, 20 January 2021 diff hist -22 Hardware Accelerator for Model Predictive Controller current
- 08:34, 20 January 2021 diff hist -23 ASIC Design of a Sigma Point Processor current
- 08:34, 20 January 2021 diff hist -23 ASIC Design of a Gaussian Message Passing Processor current
- 11:50, 12 November 2020 diff hist +387 Integrated Information Processing
- 10:38, 11 September 2020 diff hist +190 PULP →22nm
- 15:08, 19 August 2020 diff hist +122 Template
- 15:06, 19 August 2020 diff hist -58 Integrated Information Processing →Theory, Algorithms, and Hardware for Beyond 5G
- 15:05, 19 August 2020 diff hist -15 Main Page →Integrated Information Processing Group (Prof. Studer)
- 15:02, 19 August 2020 diff hist -10 Main Page →Integrated Information Processing Group (Prof. Studer)
- 15:01, 19 August 2020 diff hist +153 Template
- 11:38, 22 July 2020 diff hist 0 PULP
- 11:38, 22 July 2020 diff hist 0 N File:Pulp slide template v1.1.pptx current
- 17:49, 21 July 2020 diff hist +86 PULP →65nm
- 18:16, 20 May 2020 diff hist +16 Timing Channel Mitigations for RISC-V Cores current
- 12:51, 17 April 2020 diff hist +131 Accurate deep learning inference using computational memory current
- 11:33, 17 April 2020 diff hist +5 A computational memory unit using phase-change memory devices current
- 11:08, 17 April 2020 diff hist +4,800 N Accurate deep learning inference using computational memory Created page with "thumb ==Short Description== For decades, conventional computers based on the von Neumann architecture have performed computation by repea..."
- 11:22, 10 January 2020 diff hist +40 Template
- 11:21, 16 December 2019 diff hist +148 PULP →130nm
- 21:41, 5 December 2019 diff hist +117 PULP →Related Chips
- 10:57, 5 November 2019 diff hist -23 Accelerators for object detection and tracking current
- 10:33, 5 November 2019 diff hist -25 A computational memory unit using phase-change memory devices
- 10:32, 5 November 2019 diff hist -557 Developing a small portable neutron detector for detecting smuggled nuclear material current
- 10:30, 5 November 2019 diff hist -23 DMA Streaming Co-processor current
- 10:29, 5 November 2019 diff hist -23 Image and Video Processing current
- 10:27, 5 November 2019 diff hist -23 PULPonFPGA: Hardware L2 Cache current