Pages with the most revisions
From iis-projects
Showing below up to 50 results in range #231 to #280.
View (previous 50 | next 50) (20 | 50 | 100 | 250 | 500)
- Harald Kröll (9 revisions)
- PULPonFPGA: Lightweight Virtual Memory Support - Physically Contiguous Memory (9 revisions)
- High performance continuous-time Delta-Sigma ADC for magnetic resonance imaging (9 revisions)
- LTE-Advanced RF Front-end Design in 28nm CMOS Technology (9 revisions)
- Hardware Accelerated Derivative Pricing (9 revisions)
- Augmenting Our IPs with AXI Stream Extensions (M/1-2S) (9 revisions)
- Integrating Hardware Accelerators into Snitch (9 revisions)
- Runtime partitioning of L1 memory in Mempool (M) (9 revisions)
- Improved Reacquisition for the 5G Cellular IoT (9 revisions)
- Gomeza old project4 (9 revisions)
- Automatic unplugging detection for Ultrasound probes (9 revisions)
- Hyper Meccano: Acceleration of Hyperdimensional Computing (9 revisions)
- Configurable Ultra Low Power LDO (9 revisions)
- OpenRISC SoC for Sensor Applications (9 revisions)
- Knowledge Distillation for Embedded Machine Learning (9 revisions)
- Extension and Evaluation of TinyDMA (1-2S/B/2-3G) (9 revisions)
- Ultrasound-EMG combined hand gesture recognition (9 revisions)
- Machine Learning for extracting Muscle features using Ultrasound 2 (9 revisions)
- Practical Reconfigurable Intelligent Surfaces (RIS) (9 revisions)
- Bandwidth Extension with Carrier Aggregation for Mobile Gigabit-Communication (9 revisions)
- HERO: TLB Invalidation (9 revisions)
- Energy Efficient SoCs (9 revisions)
- Improved State Estimation on PULP-based Nano-UAVs (9 revisions)
- Design of a 25 Gbps SerDes for optical chip-to-chip communication (9 revisions)
- Real-Time Pedestrian Detection For Privacy Enhancement (9 revisions)
- Low-Energy Cluster-Coupled Vector Coprocessor for Special-Purpose PULP Acceleration (9 revisions)
- Time and Frequency Synchronization in LTE Cat-0 Devices (9 revisions)
- Efficient Implementation of an Active-Set QP Solver for FPGAs (9 revisions)
- Minimal Cost RISC-V core (9 revisions)
- DC-DC Buck converter in 65nm CMOS (9 revisions)
- Real-time eye movement analysis on a tablet computer (9 revisions)
- Karim Badawi (9 revisions)
- Investigation of Metal Diffusion in Oxides for CBRAM Applications (8 revisions)
- Sandro Belfanti (8 revisions)
- Analog Compute-in-Memory Accelerator Interface and Integration (8 revisions)
- A Unified Compute Kernel Library for Snitch (1-2S) (8 revisions)
- SCMI Support for Power Controller Subsystem (8 revisions)
- Autonomous Smart Watches: Toward an ultra low power microphone detector with events classification (8 revisions)
- EvalEDGE: A 2G Cellular Transceiver FMC (8 revisions)
- A Trustworthy Three-Factor Authentication System (8 revisions)
- Audio Video Preprocessing In Parallel Ultra Low Power Platform (8 revisions)
- Linux Driver for fine-grain and low overhead access to on-chip performance counters (8 revisions)
- Fast Wakeup From Deep Sleep State (8 revisions)
- Manycore System on FPGA (M/S/G) (8 revisions)
- Implementation of a Cache Reliability Mechanism (1S/M) (8 revisions)
- Machine Learning on Ultrasound Images (8 revisions)
- Evaluating the RiscV Architecture (8 revisions)
- Resource Partitioning of RPC DRAM (8 revisions)
- Hypervisor Extension for Ariane (M) (8 revisions)
- Resource-Constrained Few-Shot Learning for Keyword Spotting (1S) (8 revisions)