Search results

• Pirmin Vogel
  ...ing and embedded heterogeneous systems on a chip with a focus on operating system, driver, runtime and programming model support for efficient and transparen
  1 KB (193 words) - 15:39, 3 March 2020
• BLISS - Battery-Less Identification System for Security
  ...bedded image processing. The ambitious goal is to build a self-sustainable system that allows simple image processing to be implemented on-board the device. ...dy the required components for building a miniature ultra-low power camera system and develop a demonstration platform based on our ULP image sensor chip (de
  4 KB (602 words) - 10:45, 31 January 2023
• Practical Reconfigurable Intelligent Surfaces (RIS)
  [[File:Image_RIS.png|400px|thumb|RIS aided wireless system.]] In [1], a RIS is used in the downlink of a MIMO system to investigate the improvement provided by these devices in terms of energy
  8 KB (1,011 words) - 12:25, 16 November 2023
• ASIC Implementation of Jammer Mitigation
  [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]
  5 KB (662 words) - 13:31, 10 May 2023
• Wearable Smart Camera With Deep Learning Algorithms For Automatic Detecion
  * Motivation to build and test a real system [[Category:System Design]]
  4 KB (519 words) - 15:41, 10 November 2020
• EEG-based drowsiness detection
  ...r acquiring and processing biosignals, powered by GAP9, an ultra-low-power System-on-Chip (SoC). BioGAP encompasses all necessary components for measuring an : 30% System assembly design
  3 KB (375 words) - 19:03, 6 December 2023
• Weak-strong massive MIMO communication with low-resolution ADCs
  [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]
  5 KB (662 words) - 13:33, 10 May 2023
• Low Power Geolocalization And Indoor Localization
  ...classification accuracy and energy efficiency and to further optimize the system. [[Category:System Design]]
  5 KB (697 words) - 13:36, 11 January 2018
• Design Of A Biomarker Assay Based On Responsive Magnetic Nanoparticles
  * Motivation to build and test a real system [[Category:System Design]]
  4 KB (500 words) - 15:48, 10 November 2020
• Probing the limits of fake-quantised neural networks
  [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]
  5 KB (659 words) - 14:08, 15 February 2024
• Switched Capacitor Based Bandgap-Reference
  [[Category:System Design]] [[Category:System Design]]
  4 KB (471 words) - 11:13, 3 May 2018
• All the flavours of FFT on MemPool (1-2S/B)
  ...L1 data-memory. Leveraging its hierarchical architecture, we can scale the system to TeraPool, a cluster of 1024 Snitch cores, having 4096 banks of shared me
  3 KB (460 words) - 18:54, 9 November 2022
• Open Power-On Chip Controller Study and Integration
  ...nodes. Computing nodes based on ARM SoCs are facing the market, as well as system based on the IBM power architecture. To create more market opportunities IB *Good computer architecture and real-time system background.
  3 KB (462 words) - 15:57, 9 September 2016
• NeuroSoC RISC-V Component (M/1-2S)
  ...euroSoC project [1] will design and demonstrate an advanced Multiprocessor System-on-Chip based on Phase Change The NeuroSoC advanced Multiprocessor System-on-Chip prototype will be developed in FD-SOI 28nm CMOS technology and
  3 KB (482 words) - 17:26, 10 January 2024
• Energy-Efficient Brain-Inspired Hyperdimensional Computing
  ...L implementation of HD computing for an EMG-based hand gesture recognition system with fast learning using much lower power than ever before. [[Category:System Design]]
  4 KB (467 words) - 13:38, 10 November 2020
• Deep Learning Based Anomaly Detection in ECG Signals Using Foundation Models
  ...ing the latest advancements in deep learning and foundational models. This system is designed to leverage the capabilities of artificial intelligence to inte ...tem that is not only highly accurate but also efficient and scalable. This system can transform current practices in cardiovascular diagnostics, making early
  6 KB (803 words) - 19:08, 14 December 2023
• Runtime partitioning of L1 memory in Mempool (M)
  ...L1 data-memory. Leveraging its hierarchical architecture, we can scale the system to TeraPool, a cluster of 1024 Snitch cores, having 4096 banks of shared me
  3 KB (490 words) - 10:38, 2 November 2023
• MemPool on HERO (1S)
  ...ure 1 shows the block diagram of HERO. It features a shared virtual memory system between host and accelerator and provides a heterogeneous compiler toolchai ...ftware to interact with a PMCA, such as MemPool. In this step, the MemPool system will be integrated and connected to HERO’s accelerator interface.
  6 KB (902 words) - 19:07, 20 January 2021
• Design of low mismatch DAC used for VAD
  Voice activity detection (VAD) is a hot topic in nowadays IoT system that can be used for keyword spotting, speech recognition and audio recordi
  1 KB (191 words) - 17:04, 24 January 2023
• A Flexible Peripheral System for High-Performance Systems on Chip (M)
  <!-- (M): A Flexible Peripheral System for High-Performance Systems on Chip --> One of the most tedious and error-prone steps is assembling a peripheral system with the required and desired IO; this usually involves adapting existing p
  11 KB (1,675 words) - 15:40, 15 March 2021

View (previous 20 | next 20) (20 | 50 | 100 | 250 | 500)