Difference between revisions of "Completed"

Revision as of 13:52, 27 April 2018

These projects have already been completed. You can take a look at the results of the project and learn more.

Analog

2017

• Charging System for Implantable Electronics

2016

• Switched Capacitor Based Bandgap-Reference
• High performance continous-time Delta-Sigma ADC for biomedical applications
• GUI-developement for an action-cam-based eye tracking device

2015

2014

2013

• Wireless Biomedical Signal Acquisition Device
• Flexible Front-End Circuit for Biomedical Data Acquisition
• High-Resolution Large-Bandwidth Delta-Sigma A/D Converters in Ultra-Scaled CMOS

2012

• Data Mapping for Unreliable Memories
• Exploitation of Inherent Error Resilience of Wireless Systems under Unreliable Silicon
• High Throughput Turbo Decoder Design
• Turbo Decoder Design for High Code Rates
• Channel Decoding for TD-HSPA
• Near-Optimal Reduced-Complexity Sequence Detectors for TD-HSPA
• A Novel Constrained-Viterbi Algorithm with Linear Equalization and Grouping Assistance
• Successive Interference Cancellation for 3G Downlink
• Channel Estimation for TD-HSPA
• Evolved EDGE Physical Layer Incremental Redundancy Architecture
• MatPHY: An Open-Source Physical Layer Development Framework
• Interference Cancellation for Evolved EDGE on the RazorEDGE baseband ASIC
• Soft-Output Viterbi Equalizer as part of Evolved EDGE baseband ASIC
• High Performance Cellular Receivers in Very Advanced CMOS
• Multi-Band Receiver Design for LTE Mobile Communication
• High-Resolution, Calibrated Folding ADCs

Digital

2017

• A computational memory unit using phase-change memory devices
• Deep Learning for Brain-Computer Interface
• Low-Energy Cluster-Coupled Vector Coprocessor for Special-Purpose PULP Acceleration
• Turbo Equalization for Cellular IoT
• Sensor Fusion for Rockfall Sensor Node
• Development of a Rockfall Sensor Node
• FPGA Optimizations of Dense Binary Hyperdimensional Computing
• Fast and Accurate Multiclass Inference for Brain–Computer Interfaces
• A Wireless Sensor Network for a Smart Building Monitor and Control
• BigPULP: Multicluster Synchronization Extensions
• Sub Noise Floor Channel Estimation for the Cellular Internet of Things
• PULPonFPGA: Lightweight Virtual Memory Support - Page Table Walker
• StoneEDGE: An EC-GSM-IoT and Evolved EDGE PHY ASIC

2016

• A Recurrent Neural Network Speech Recognition Chip
• Efficient NB-IoT Uplink Design
• Internet of Things Network Synchronizer
• Accelerator for Boosted Binary Features
• Accelerator for Spatio-Temporal Video Filtering
• Interfacing PULP with a Brain-Inspired Ultra-Low Power Spiking Cochlea
• Design and Implementation of Digital Spiking Neurons for Ultra-Low-Power In-Cluster Coprocessors
• System Analysis and VLSI Design of NB-IoT Baseband Processing
• High-speed Scene Labeling on FPGA
• Learning Image Decompression with Convolutional Networks
• FPGA System Design for Computer Vision with Convolutional Neural Networks
• PULPonFPGA: Lightweight Virtual Memory Support - Multi-Level TLB
• Implementing Hibernation on the ARM Cortex M0
• High-Throughput Hardware Implementations of Authenticated Encryption Algorithms
• Spatio-Temporal Video Filtering
• PULPonFPGA: Lightweight Virtual Memory Support - Coherency Extensions

2015

• Hardware Accelerated Derivative Pricing
• Glitches Reduce Listening Time of Your iPod
• FFT-based Convolutional Network Accelerator
• Real-Time Optical Flow Using Neural Networks
• EvaLTE: A 2G/3G/4G Cellular Transceiver FMC
• Synchronisation and Cyclic Prefix Handling For LTE Testbed
• An FPGA-Based Testbed for 3G Mobile Communications Receivers
• Reading The GSM Beacon Carrier with OsmocomBB and stoneEDGE
• Baseband Meets CPU
• Active-Set QP Solver on FPGA
• Vector Processor for In-Memory Computing
• StoneEDGE: An EC-GSM-IoT and Evolved EDGE PHY ASIC
• Hardware/software co-programming on the Parallella platform
• Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA
• Time and Frequency Synchronization in LTE Cat-0 Devices
• Real-Time Stereo to Multiview Conversion

2014

• EvalEDGE: A 2G Cellular Transceiver FMC
• Real-Time Stereo to Multiview Conversion
• Design and Implementation of a Convolutional Neural Network Accelerator ASIC
• Design and Implementation of an Approximate Floating Point Unit

2013

• RazorEDGE: An Evolved EDGE DBB ASIC
• Real-Time Stereo to Multiview Conversion
• NORX - an AEAD algorithm for the CAESAR competition
• A Unified-Multiplier Based Hardware Architecture for Elliptic Curve Cryptography
• SHAre - An application Specific Instruction Set Processor for SHA-2/3
• Quantum Key Secured 100 Gbit/s Payload Encryption and its High-Speed Network Interfaces
• Feature Extraction with Binarized Descriptors: ASIC Implementation and FPGA Environment
• Real-time View Synthesis using Image Domain Warping
• Ultra-low power processor design

2012

• A Multiview Synthesis Core in 65 nm CMOS
• Real-time View Synthesis using Image Domain Warping
• High-Throughput Authenticated Encryption Architectures based on Block Ciphers

Nano Electronics

2016

2015

2014

2013

2012

Nano TCAD

2016

2015

2014

2013

2012