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Deep Learning Projects

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Revision as of 18:27, 1 November 2017 by Lukasc (talk | contribs) (Projects)
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We are listing a few projects below to give you an idea of what we do. However, we constantly have new project ideas and maybe some other approaches become obsolete in the very rapidly advancing research area. Please just contact the people of a project most similar to what you would like to do, and come talk to us.

Prerequisites

We have no strict, general requirements, as they are highly dependent on the exact project steps. The projects will be adapted to the skills and interests of the student(s) -- just come talk to us! If you don't know about GPU programming or CNNs or ... just let us know and we can together determine what is a useful way to go -- after all you are here to learn not only about project work, but also to develop your technical skills.

Only hard requirements:

  • Excitement for deep learning
  • For VLSI projects: VLSI 1 or equivalent

Projects

Project Name Description Platform Workload Type Contact(s)
CBinfer+ Running CNNs to a large extent means a tremendous computational effort, particularly when looking at object detection and image segmentation. For many applications we want to run everything in real-time on video data. We exploit that only few pixels change from frame to frame (cf. paper). We have several ideas on a) how to improve the algorithm, and b) would like to optimize the implementation for the next generation of (embedded) GPUs. You can be part of this (already successful) research path. Embedded GPU (Tegra X2) SW (GPU, algo evals) Lukas Cavigelli
CBinfer HW The motiviation here is the same as for CBinfer+. Here we want to build a custom hardware architecture for ASICs capable of running this type of workload. ASIC HW (ASIC) Lukas Cavigelli
Distributed/Federated Learning Example Example Example
The Always-On Self-Learning Camera Node Example Example Example
XXXXXXXXXXXXXXXXX Example Example Example
Example Example Example Example


Workload types: SW (GPU), SW (microcontr.), SW (algorithm evals), HW (FPGA), HW (ASIC), HW (PCB)