Difference between revisions of "Design and Implementation of a Convolutional Neural Network Accelerator ASIC"
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: Explore various architectures to perform the 2D convolutions used in convolutional networks, considering the constraints of an ASIC design, and performing fixed-point analyses for the most viable architecture(s) | : Explore various architectures to perform the 2D convolutions used in convolutional networks, considering the constraints of an ASIC design, and performing fixed-point analyses for the most viable architecture(s) | ||
: Get to know the ASIC design flow from specification through architecture exploration to implementation, functional verification, back-end design and silicon testing. | : Get to know the ASIC design flow from specification through architecture exploration to implementation, functional verification, back-end design and silicon testing. | ||
+ | |||
+ | ===Step-by-Step Workflow=== | ||
+ | 1. Get to understand the basic concepts of convolutional networks. | ||
+ | 2. Catch up on relevant previous work, in particular the papers we give to you. | ||
+ | 3. Become aware of the possibilities and limitations of the used technology; make some very rough estimates of area and timing. Also consider setting some target specifications for your chip. | ||
+ | 4. Come up with and evaluate/discuss several possible architectures (architecture exploration), implement the datapath/most resource relevant parts to get some first impression of the most promissing architecture(s). Also give some first thoughts to testability. | ||
+ | 5. Run detailed fixed-point analyses to determine the signal width in all parts of the data path. | ||
+ | 6. Create high quality, synthesizable VHDL code for your circuit. Please respect the lab's coding guidelines and continuously verify proper functionality of the individual parts of your design. | ||
+ | 7. Implement the necessary configuration interface, ... | ||
+ | 8. Perform thorough functional verification. This is very important. | ||
+ | 9. Take your final implementation through the backend design process. | ||
+ | 10. xx | ||
+ | |||
+ | Be aware, that these steps cannot always be performed one after the other and often need some initial guesses and | ||
+ | config interface | ||
===Literature=== | ===Literature=== |
Revision as of 18:01, 16 December 2014
Contents
Short Description
Imaging sensor networks, UAVs, smartphones, and other embedded computer vision systems require power-efficient, low-cost and high-speed implementations of synthetic vision systems capable of recognizing and classifying objects in a scene. Many popular algorithms in this area require the evaluations of multiple layers of filter banks. Almost all state-of-the-art synthetic vision systems are based on features extracted using multi-layer convolutional networks (ConvNets). When evaluating ConvNets, most of the time is spent performing the convolutions (80% to 90%). The focus of this work is on speeding up this step by creating an accelerator to perform this step faster and more power-efficiently.
Status: In Progress
- David Gschwend, Christoph Mayer, Samuel Willi
- Supervision: Lukas Cavigelli, Beat Muheim
- Date: Fall Semester 2014 (sem14h17, sem14h18, sem14h19)
Prerequisites
- Knowledge of Matlab
- Interest in video processing and VLSI design
- VLSI 1 and enrolment in VLSI 2 is required
- At least one student has to test the chip as part of the VLSI 3 lecture, if the ASIC should be manufactured.
Character
- 10% Theory / Literature Research
- 60% VLSI Architecture, Implementation & Verification
- 30% VLSI back-end Design
Professor
Detailed Task Description
Goals
- Explore various architectures to perform the 2D convolutions used in convolutional networks, considering the constraints of an ASIC design, and performing fixed-point analyses for the most viable architecture(s)
- Get to know the ASIC design flow from specification through architecture exploration to implementation, functional verification, back-end design and silicon testing.
Step-by-Step Workflow
1. Get to understand the basic concepts of convolutional networks. 2. Catch up on relevant previous work, in particular the papers we give to you. 3. Become aware of the possibilities and limitations of the used technology; make some very rough estimates of area and timing. Also consider setting some target specifications for your chip. 4. Come up with and evaluate/discuss several possible architectures (architecture exploration), implement the datapath/most resource relevant parts to get some first impression of the most promissing architecture(s). Also give some first thoughts to testability. 5. Run detailed fixed-point analyses to determine the signal width in all parts of the data path. 6. Create high quality, synthesizable VHDL code for your circuit. Please respect the lab's coding guidelines and continuously verify proper functionality of the individual parts of your design. 7. Implement the necessary configuration interface, ... 8. Perform thorough functional verification. This is very important. 9. Take your final implementation through the backend design process. 10. xx
Be aware, that these steps cannot always be performed one after the other and often need some initial guesses and config interface
Literature
Practical Details
Results
Links
- The EDA wiki with lots of information on the ETHZ ASIC design flow (internal only) [1]