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Design and Implementation of a Convolutional Neural Network Accelerator ASIC

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Short Description

todo

Status: In Progress

David Gschwend, Christoph Mayer, Samuel Willi
Supervision: Lukas Cavigelli, Beat Muheim
Date: Fall Semester 2014 (sem14h17, sem14h18, sem14h19)

Prerequisites

Knowledge of Matlab
Interest in video processing and VLSI design
VLSI 1 and enrolment in VLSI 2 is required
At least one student has to test the chip as part of the VLSI 3 lecture, if the ASIC should be manufactured.


Character

10% Theory / Literature Research
60% VLSI Architecture, Implementation & Verification
30% VLSI back-end Design

Professor

Luca Benini

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