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(Top: High-level architecture of the channel decoding chain for the downlink terminal side of 3GPP TD-HSPA. Bottom: Layout of the fabricated turbo and Viterbi decoder prototypes integrated in 180 nm CMOS technology.)
 
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Latest revision as of 10:10, 4 February 2014

Top: High-level architecture of the channel decoding chain for the downlink terminal side of 3GPP TD-HSPA. Bottom: Layout of the fabricated turbo and Viterbi decoder prototypes integrated in 180 nm CMOS technology.

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current10:10, 4 February 2014Thumbnail for version as of 10:10, 4 February 2014631 × 517 (300 KB)Kgf (talk | contribs)Top: High-level architecture of the channel decoding chain for the downlink terminal side of 3GPP TD-HSPA. Bottom: Layout of the fabricated turbo and Viterbi decoder prototypes integrated in 180 nm CMOS technology.
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Horizontal resolution 118.11 dpc
Vertical resolution 118.11 dpc
File change date and time 08:10, 4 February 2014
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