View source for Modeling High Bandwidth Memory for Rapid Design Space Exploration (1-3S/B)

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[[Category:Digital]]
[[Category:High Performance SoCs]]
[[Category:Computer Architecture]]
[[Category:2022]]
[[Category:Semester Thesis]]
[[Category:Tbenz]]
[[Category:Available]]


= Overview =

== Status: Available ==

* Type: Bachelor / Semester Thesis 
* Professor: Prof. Dr. L. Benini
* Supervisors:
** [[:User:Tbenz | Thomas Benz]]: [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]

= Introduction =


We recently taped Occamy in 12nm featuring a High Bandwidth Memory (HBM) controller. Simulations of the chip with the HBM active require multiple orders of magnitude more time than a regular RTL-only simulation due to the complexity of the HBM subsystem.

= Project =

We would like to characterize the HBM subsystem, gaining key figures of merits like throughput, latency, etc. in the process. We then use these numbers to create a simple simulation-only (or RTL unit) that mimics the behavior of HBM but operates much faster in simulation.


== Character ==
10% Research HBM and DRAM technology
40% Simulation of the HBM, characterization, and model-building
20% Implementation of the model in SV 
30% Evaluation 

== Prerequisites ==

* Interest in memory systems
* Experience with digital design in SystemVerilog as taught in VLSI I
* Preferred: Knowledge of AXI4

= References =