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| − | <!-- Radiation Testing Board (1S) -->
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| − | [[Category:Digital]]
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| − | [[Category:Fault Tolerance]]
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| − | [[Category:HW/SW Safety and Security]]
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| − | [[Category:2022]]
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| − | [[Category:Semester Thesis]]
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| − | [[Category:Michaero]]
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| − | [[Category:Available]]
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| − | = Overview =
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| − | == Status: Available ==
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| − | * Type: Semester Thesis
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| − | * Professor: Prof. Dr. L. Benini
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| − | * Supervisors:
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| − | ** [[:User:Michaero | Michael Rogenmoser]]: [mailto:michaero@iis.ee.ethz.ch michaero@iis.ee.ethz.ch]
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| − | ** [[:User:Kgf | Frank Gurkaynak]]: [mailto:kgf@iis.ee.ethz.ch kgf@iis.ee.ethz.ch]
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| − | = Introduction =
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| − | At IIS, we recently taped out two ASICs with features for fault tolerance, increasing redundancy to radiation-induced errors, e.g. for Space applications.
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| − | After these Chips ([http://asic.ethz.ch/2022/Cerberus.html Cerberus] and [http://asic.ethz.ch/2022/Trikarenos.html Trikarenos]) are brought up once they return from being manufactured, we would like to test them under a radiation beam.
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| − | = Project =
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| − | In this project, an independent testing infrastructure for the two chips will be developed, allowing for testing in a sealed chamber under a radiation beam. As this chamber only provides limited access, a reliable stand-alone infrastructure is required. This includes:
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| − | * An overall test setup, picking the devices to control and interface with the chips
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| − | * software for a simple computer to reliably control and program the chip, and log any errors
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| − | * Time-permitting, a PCB for the chips, providing power and clock and interface options
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| − | As the chips are not back from manufacturing yet, the testing infrastructure will initially be deployed with an FPGA port of the chip for debugging.
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| − | == Character ==
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| − | * 30% System design
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| − | * 50% Software design (scripting, C, python)
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| − | * 20% PCB design
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| − | == Prerequisites ==
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| − | * Familiarity with ASIC design and testing is beneficial
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| − | * Experience with PCB design is beneficial
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