|
|
(One intermediate revision by the same user not shown) |
Line 1: |
Line 1: |
− | <!-- Radiation Testing Board (1S) -->
| + | #REDIRECT [[Radiation Testing of a PULP ASIC]] |
− | | |
− | [[Category:Digital]]
| |
− | [[Category:Fault Tolerance]]
| |
− | [[Category:HW/SW Safety and Security]]
| |
− | [[Category:2022]]
| |
− | [[Category:Semester Thesis]]
| |
− | [[Category:Michaero]]
| |
− | [[Category:Available]]
| |
− | | |
− | | |
− | = Overview =
| |
− | | |
− | == Status: Available ==
| |
− | | |
− | * Type: Semester Thesis
| |
− | * Professor: Prof. Dr. L. Benini
| |
− | * Supervisors:
| |
− | ** [[:User:Michaero | Michael Rogenmoser]]: [mailto:michaero@iis.ee.ethz.ch michaero@iis.ee.ethz.ch]
| |
− | ** [[:User:Kgf | Frank Gurkaynak]]: [mailto:kgf@iis.ee.ethz.ch kgf@iis.ee.ethz.ch]
| |
− | | |
− | = Introduction =
| |
− | | |
− | At IIS, we recently taped out two ASICs with features for fault tolerance, increasing redundancy to radiation-induced errors, e.g. for Space applications.
| |
− | | |
− | After these Chips ([http://asic.ethz.ch/2022/Cerberus.html Cerberus] and [http://asic.ethz.ch/2022/Trikarenos.html Trikarenos]) are brought up once they return from being manufactured, we would like to test them under a radiation beam.
| |
− | | |
− | = Project =
| |
− | | |
− | In this project, an independent testing infrastructure for the two chips will be developed, allowing for testing in a sealed chamber under a radiation beam. As this chamber only provides limited access, a reliable stand-alone infrastructure is required. This includes:
| |
− | * An overall test setup, picking the devices to control and interface with the chips
| |
− | * software for a simple computer to reliably control and program the chip, and log any errors
| |
− | * Time-permitting, a PCB for the chips, providing power and clock and interface options
| |
− | | |
− | As the chips are not back from manufacturing yet, the testing infrastructure will initially be deployed with an FPGA port of the chip for debugging.
| |
− | | |
− | == Character ==
| |
− | | |
− | * 30% System design
| |
− | * 50% Software design (scripting, C, python)
| |
− | * 20% PCB design
| |
− | | |
− | == Prerequisites ==
| |
− | | |
− | * Familiarity with ASIC design and testing is beneficial
| |
− | * Experience with PCB design is beneficial
| |