Difference between revisions of "Research"
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Revision as of 16:23, 18 February 2015
Research projects at the Integrated Systems Laboratory (IIS).
2015
- EvaLTE: A 2G/3G/4G Cellular Transceiver FMC
- Vector Processor for In-Memory Computing
- StoneEDGE: An EC-GSM-IoT and Evolved EDGE PHY ASIC
2014
2013
- RazorEDGE: An Evolved EDGE DBB ASIC
- Wireless Biomedical Signal Acquisition Device
- Flexible Front-End Circuit for Biomedical Data Acquisition
- High-Resolution Large-Bandwidth Delta-Sigma A/D Converters in Ultra-Scaled CMOS
- Real-time View Synthesis using Image Domain Warping
- Quantum Key Secured 100 Gbit/s Payload Encryption and its High-Speed Network Interfaces
- SHAre - An application Specific Instruction Set Processor for SHA-2/3
2012
- A Multiview Synthesis Core in 65 nm CMOS
- Data Mapping for Unreliable Memories
- Exploitation of Inherent Error Resilience of Wireless Systems under Unreliable Silicon
- High Throughput Turbo Decoder Design
- Turbo Decoder Design for High Code Rates
- Channel Decoding for TD-HSPA
- Near-Optimal Reduced-Complexity Sequence Detectors for TD-HSPA
- A Novel Constrained-Viterbi Algorithm with Linear Equalization and Grouping Assistance
- Successive Interference Cancellation for 3G Downlink
- Channel Estimation for TD-HSPA
- Evolved EDGE Physical Layer Incremental Redundancy Architecture
- MatPHY: An Open-Source Physical Layer Development Framework
- Interference Cancellation for Evolved EDGE on the RazorEDGE baseband ASIC
- Soft-Output Viterbi Equalizer as part of Evolved EDGE baseband ASIC
- High Performance Cellular Receivers in Very Advanced CMOS
- Multi-Band Receiver Design for LTE Mobile Communication
- High-Resolution, Calibrated Folding ADCs
- Real-time View Synthesis using Image Domain Warping
