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- 17:30, 17 November 2021 (diff | hist) . . (+3,968) . . N Streaming Integer Extensions for Snitch (M) (Created page with "<!-- Universal Stream Semantic Registers for Snitch (1S) --> Category:Digital Category:High Performance SoCs Category:Computer Architecture Category:Acceleratio...")
- 17:03, 17 November 2021 (diff | hist) . . (+88) . . Augmenting Our IPs with AXI Stream Extensions (M/1-2S) (→Prerequisites)
- 15:51, 17 November 2021 (diff | hist) . . (-4) . . Transforming MemPool into a CGRA (M) (current)
- 15:50, 17 November 2021 (diff | hist) . . (-2) . . Multi issue OoO Ariane Backend (M) (current)
- 15:43, 17 November 2021 (diff | hist) . . (+3,121) . . N Augmenting Our IPs with AXI Stream Extensions (M/1-2S) (Created page with "<!-- Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S) --> Category:Digital Category:High Performance SoCs Category:Computer Architecture Catego...")
- 20:13, 15 November 2021 (diff | hist) . . (+3) . . Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S) (→Status: Reserved)
- 20:02, 15 November 2021 (diff | hist) . . (-50) . . IP-Based SoC Generation and Configuration (1-3S/B) (→Introduction)
- 19:47, 15 November 2021 (diff | hist) . . (+766) . . IP-Based SoC Generation and Configuration (1-3S/B)
- 13:08, 15 November 2021 (diff | hist) . . (-83) . . Analog Compute-in-Memory Accelerator Interface and Integration
- 13:04, 15 November 2021 (diff | hist) . . (-1) . . High Performance SoCs (→Who are we)
- 21:35, 4 October 2021 (diff | hist) . . (+3) . . m Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S)
- 22:18, 14 September 2021 (diff | hist) . . (-2) . . Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S)
- 17:03, 9 September 2021 (diff | hist) . . (-3) . . m High Performance SoCs (→Projects)
- 15:48, 9 September 2021 (diff | hist) . . (+654) . . High Performance SoCs (→Projects)
- 15:10, 10 August 2021 (diff | hist) . . (0) . . m Exploration and Hardware Acceleration of Intra-Layer Mixed-Precision QNNs (→Status: Available)
- 15:08, 10 August 2021 (diff | hist) . . (+3,465) . . N Exploration and Hardware Acceleration of Intra-Layer Mixed-Precision QNNs (Created page with "<!-- Exploration and Hardware Acceleration of Intra-Layer Mixed-Precision QNNs --> Category:Digital Category:Deep Learning Projects Category:Acceleration_and_Transp...")
- 14:52, 10 August 2021 (diff | hist) . . (+45) . . Universal Stream Semantic Registers for Snitch (1S)
- 13:25, 10 August 2021 (diff | hist) . . (+7) . . m Evaluating memory access pattern specializations in OoO, server-grade cores (M) (current)
- 13:24, 10 August 2021 (diff | hist) . . (-29) . . Universal Stream Semantic Registers for Snitch (1S)
- 13:24, 10 August 2021 (diff | hist) . . (-27) . . Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S)
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