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Showing below up to 100 results in range #251 to #350.
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- VLSI Implementation of a Systolic Array for LMMSE Detection in mmWave Massive MIMO-OFDM (4 revisions)
- Near-Memory Training of Neural Networks (4 revisions)
- Intelligent Power Management Unit (iPMU) (4 revisions)
- Positioning for the cellular Internet of Things (4 revisions)
- Improving our Smart Camera System (4 revisions)
- Ibex: Bit-Manipulation Extension (4 revisions)
- Variability Tolerant Ultra Low Power Cluster (4 revisions)
- An FPGA-Based Testbed for 3G Mobile Communications Receivers (4 revisions)
- Enhancing our DMA Engine with Fault Tolerance (4 revisions)
- Smart Wearable System For Vital Sign Monitoring Exploiting On Board and Cloud Machine Learning (4 revisions)
- Super Resolution Radar/Imaging at mm-Wave frequencies (4 revisions)
- Wireless Biomedical Signal Acquisition Device (4 revisions)
- FPGA-based Implementation of a Novel Cell-Search Algorithm for Mobile Communications (4 revisions)
- Spiking Neural Network for Motor Function Decoding Based on Neural Dust (4 revisions)
- Hardware Exploration of Shared-Exponent MiniFloats (M) (4 revisions)
- In-ear EEG signal acquisition (4 revisions)
- CPS Software-Configurable State-Machine (4 revisions)
- Theory, Algorithms, and Hardware for Beyond 5G (4 revisions)
- ASIC Design of a Sigma Point Processor (4 revisions)
- A Wearable Wireless Kidney Function Monitoring System For BioMedical Applications (4 revisions)
- Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B) (4 revisions)
- Smart e-glasses for concealed recording of EEG signals (4 revisions)
- Accelerating Applications Relying on Matrix-Vector-Product-Like Operations (4 revisions)
- Power Optimization in Multipliers (4 revisions)
- Low-power chip-to-chip communication network (4 revisions)
- Final Report (4 revisions)
- High performance continous-time Delta-Sigma ADC for biomedical applications (4 revisions)
- Coherence-Capable Write-Back L1 Data Cache for Ariane (4 revisions - redirect page)
- Forward error-correction ASIC using GRAND (4 revisions)
- A Snitch-Based SoC on iCE40 FPGAs (1-2S/B) (4 revisions)
- Students' Interanational Competitions: F1(AMZ), Swissloop, Educational Rockets (4 revisions)
- Accelerating Stencil Workloads on Snitch using ISSRs (1-2S/B) (4 revisions)
- Adding Linux Support to our DMA engine (1-2S/B) (4 revisions - redirect page)
- SHAre - An application Specific Instruction Set Processor for SHA-2/3 (4 revisions)
- Eye movements (4 revisions)
- Palm size chip NMR (4 revisions)
- Implementation of an AES Hardware Processing Engine (B/S) (4 revisions)
- Telecommunications (4 revisions)
- Influence of the Initial FilamentGeometry on the Forming Step in CBRAM (4 revisions)
- Smart Goggles for Visual In-Action Feedback in Ski Jumping (1 B/S) (4 revisions)
- NAND Flash Open Research Platform (4 revisions)
- Ultra-low power sampling front-end for acquisition of physiological signals (4 revisions)
- Finite element modeling of electrochemical random access memory (4 revisions)
- Ultrasound High Speed Microbubble Tracking (4 revisions)
- EEG artifact detection with machine learning (4 revisions)
- Stefan Lippuner (4 revisions)
- Advanced Data Movers for Modern Neural Networks (4 revisions)
- Virtual Memory Ara (4 revisions)
- Efficient TNN compression (4 revisions)
- Jammer-Resilient Synchronization for Wireless Communications (4 revisions)
- SSR combined with FREP in LLVM/Clang (M/1-3S) (4 revisions - redirect page)
- Sub-Noise Floor Channel Tracking (4 revisions)
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RI5CY core (4 revisions)
- Pascal Hager (4 revisions)
- RISC-V based Implementation of Secure Ranging According to IEEE 802.15.4z UWB (5 revisions)
- Internet of Things SoC Characterization (5 revisions)
- Ternary Neural Networks for Face Recognition (5 revisions)
- A Unified-Multiplier Based Hardware Architecture for Elliptic Curve Cryptography (5 revisions)
- Precise Ultra-low-power Timer (5 revisions)
- Smart Googles for Visual In-Action Feedback in Ski Jumping (1 B/S) (5 revisions)
- Embedded Systems and autonomous UAVs (5 revisions)
- LightProbe - Thermal-Power aware on-head Beamforming (5 revisions)
- Data Augmentation Techniques in Biosignal Classification (5 revisions)
- IP-Based SoC Generation and Configuration (1-3S/B) (5 revisions)
- Predict eye movement through brain activity (5 revisions)
- Subject specific embeddings for transfer learning in brain-computer interfaces (5 revisions)
- Design of a Prototype Chip with Interleaved Memory and Network-on-Chip (5 revisions)
- Hardware Accelerator for Model Predictive Controller (5 revisions)
- Noise Figure Measurement for Cryogenic System (5 revisions)
- An Energy Efficient Brain-Computer Interface using Mr.Wolf (5 revisions)
- Engineering For Kids (5 revisions)
- Control an external ADC using Programmable Real-Time Unit (PRU) Subsystem on Beaglebone Black used as embedded HPC-performance-monitoring device (5 revisions)
- Toward Superposition of Brain-Computer Interface Models (5 revisions)
- Ultra Low Power Conversion Circuit For Batteryless Applications (5 revisions)
- Low Power One bit Microphone for Acoustic Imaging Using A Parallel Processor (5 revisions)
- ASIC Design Projects (5 revisions)
- A Wearable System To Control Phone And Electronic Device Without Hands (5 revisions)
- Predictable Execution on GPU Caches (5 revisions)
- Federico Villani (5 revisions)
- Toward hyperdimensional active perception: learning compressed sensorimotor control by demonstration (5 revisions)
- Ultra Low Power Wake Up Radio for Wireless Sensor Network (5 revisions)
- Design and Implementation of ultra low power vision system (5 revisions)
- Ultrasound signal processing acceleration with CUDA (5 revisions)
- Fast Simulation of Manycore Systems (1S) (5 revisions)
- WCDMA/HSPA+ Synchronization System Design, Implementation, and Testing (5 revisions)
- Pressure and acoustic Smart Sensors Network for Wind Turbines Monitoring (5 revisions)
- Low-power Clock Generation Solutions for 65nm Technology (5 revisions)
- Ferroelectric Memristors for Artificial Neural Networks (IBM-Zurich) (5 revisions)
- Towards Autonomous Navigation for Nano-Blimps (5 revisions)
- On-Device Training Sparse Sub-Tensor Update Scheme Optimization for CNN-based tasks (SA or MA) (5 revisions)
- Interfacing PULP with a Brain-Inspired Ultra-Low Power Spiking Cochlea (5 revisions)
- TCNs vs. LSTMs for Embedded Platforms (5 revisions)
- Compression of Ultrasound data on FPGA (5 revisions)
- High-Speed SAR ADC for next generation wireless communication in 12nm FinFET (5 revisions)
- Electrothermal characterization of van der Waals Heterostructures with a partial overlap (5 revisions)
- Final Presentation (5 revisions)
- Switched-capacitor power amplifier for IoT mobile communications: design of signal processing path (5 revisions)
- Ultrafast Medical Ultrasound imaging on a GPU (5 revisions)
- Next-Gen Ultrasound Imaging Systems (Industry Student Projects & PhD Opportunity) (5 revisions)
- Universal Stream Semantic Registers for Snitch (1S) (5 revisions - redirect page)
