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Showing below up to 50 results in range #251 to #300.
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- VLSI Implementation of a Systolic Array for LMMSE Detection in mmWave Massive MIMO-OFDM (4 revisions)
- Near-Memory Training of Neural Networks (4 revisions)
- Intelligent Power Management Unit (iPMU) (4 revisions)
- Positioning for the cellular Internet of Things (4 revisions)
- Improving our Smart Camera System (4 revisions)
- Ibex: Bit-Manipulation Extension (4 revisions)
- Variability Tolerant Ultra Low Power Cluster (4 revisions)
- An FPGA-Based Testbed for 3G Mobile Communications Receivers (4 revisions)
- Enhancing our DMA Engine with Fault Tolerance (4 revisions)
- Smart Wearable System For Vital Sign Monitoring Exploiting On Board and Cloud Machine Learning (4 revisions)
- Super Resolution Radar/Imaging at mm-Wave frequencies (4 revisions)
- Wireless Biomedical Signal Acquisition Device (4 revisions)
- FPGA-based Implementation of a Novel Cell-Search Algorithm for Mobile Communications (4 revisions)
- Spiking Neural Network for Motor Function Decoding Based on Neural Dust (4 revisions)
- Hardware Exploration of Shared-Exponent MiniFloats (M) (4 revisions)
- In-ear EEG signal acquisition (4 revisions)
- CPS Software-Configurable State-Machine (4 revisions)
- Theory, Algorithms, and Hardware for Beyond 5G (4 revisions)
- ASIC Design of a Sigma Point Processor (4 revisions)
- A Wearable Wireless Kidney Function Monitoring System For BioMedical Applications (4 revisions)
- Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B) (4 revisions)
- Smart e-glasses for concealed recording of EEG signals (4 revisions)
- Accelerating Applications Relying on Matrix-Vector-Product-Like Operations (4 revisions)
- Power Optimization in Multipliers (4 revisions)
- Low-power chip-to-chip communication network (4 revisions)
- Final Report (4 revisions)
- High performance continous-time Delta-Sigma ADC for biomedical applications (4 revisions)
- Coherence-Capable Write-Back L1 Data Cache for Ariane (4 revisions - redirect page)
- Forward error-correction ASIC using GRAND (4 revisions)
- A Snitch-Based SoC on iCE40 FPGAs (1-2S/B) (4 revisions)
- Students' Interanational Competitions: F1(AMZ), Swissloop, Educational Rockets (4 revisions)
- Accelerating Stencil Workloads on Snitch using ISSRs (1-2S/B) (4 revisions)
- Adding Linux Support to our DMA engine (1-2S/B) (4 revisions - redirect page)
- SHAre - An application Specific Instruction Set Processor for SHA-2/3 (4 revisions)
- Eye movements (4 revisions)
- Palm size chip NMR (4 revisions)
- Implementation of an AES Hardware Processing Engine (B/S) (4 revisions)
- Telecommunications (4 revisions)
- Influence of the Initial FilamentGeometry on the Forming Step in CBRAM (4 revisions)
- Smart Goggles for Visual In-Action Feedback in Ski Jumping (1 B/S) (4 revisions)
- NAND Flash Open Research Platform (4 revisions)
- Ultra-low power sampling front-end for acquisition of physiological signals (4 revisions)
- Finite element modeling of electrochemical random access memory (4 revisions)
- Ultrasound High Speed Microbubble Tracking (4 revisions)
- EEG artifact detection with machine learning (4 revisions)
- Stefan Lippuner (4 revisions)
- Advanced Data Movers for Modern Neural Networks (4 revisions)
- Virtual Memory Ara (4 revisions)
- Efficient TNN compression (4 revisions)
- Jammer-Resilient Synchronization for Wireless Communications (4 revisions)
