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From iis-projects
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Date | Name | Thumbnail | Size | Description | Versions |
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11:38, 22 July 2020 | Pulp slide template v1.1.pptx (file) | 1.43 MB | 1 | ||
10:18, 10 March 2016 | Latex template.tar.gz (file) | 1.08 MB | 1 | ||
21:36, 30 January 2018 | PhysXilinxBoard.png (file) | 1.01 MB | 1 | ||
15:57, 17 November 2015 | Standard Cell Compatible Memory Array Design.png (file) | 942 KB | Concept of the standard cell compatible memory array. | 1 | |
18:28, 28 January 2014 | Madmax explanations.png (file) | 830 KB | 1 | ||
10:24, 4 February 2014 | High Throughput Turbo Decoder Design.png (file) | 804 KB | Chip micrograph of the LTE-Advanced turbo decoder. The overlay depicts the exact locations of the 16 parallel SISO decoders used to achieve the 1Gbps throughput. | 1 | |
20:15, 26 January 2023 | Ifduot.jpg (file) | 720 KB | 1 | ||
13:32, 27 March 2014 | The default funny picture here.jpg (file) | 622 KB | 1 | ||
18:26, 29 January 2014 | Simplified trellis as used in the SOVE algorithm.png (file) | 617 KB | Top: Simplified trellis as used in the SOVE algorithm. Bottom: Layout of the RazorEDGE physical layer baseband ASIC. The highlighted area is occupied by the SOVE block. | 1 | |
16:17, 24 June 2017 | IBM Phase Change Memory.png (file) | 574 KB | 1 | ||
18:16, 28 January 2014 | Warping example.png (file) | 528 KB | Aspect ratio retargeting example illustrating the image domain warping steps: from an initial regular grid, we generate a spatially-varying warp grid that is used to warp the image. Original image: Courtesy of Andrew Malone (CC). | 1 | |
18:01, 29 January 2014 | Chip Micrograph of Cerebrov2.png (file) | 493 KB | Chip micrograph of the 8-channel sensor front-end and data acquisition IC ‘Cerebro v2’ for electrode-based medical applications, such as ECG or EEG. Implemented in a 130 nm CMOS technology. | 1 | |
20:00, 27 January 2021 | Yourchip.jpg (file) | 492 KB | Dustin | 1 | |
18:15, 29 January 2014 | Battery powered medical signal acquisition platform.png (file) | 481 KB | 1 | ||
19:48, 21 May 2015 | Switched capacitor based bandgap.png (file) | 480 KB | Taken from Shrivastava, et. al., "A 32nW Bandgap Reference Voltage Operational from 0.5V Supply for Ultra-Low Power Systems", ISSCC 2015 | 1 | |
15:54, 14 January 2015 | Pulp Efficient Supply.jpg (file) | 473 KB | Power management design | 1 | |
16:36, 21 June 2018 | SolidStatePhysics.png (file) | 470 KB | 1 | ||
12:05, 17 January 2014 | Assesment of novel photovoltaic architectures.jpg (file) | 455 KB | 1 | ||
19:13, 16 January 2014 | High-Speed DigRF-v4 Implementation.png (file) | 397 KB | 1 | ||
08:56, 21 October 2019 | Pulp slide template v1.0.pptx (file) | 361 KB | There was a strange information in the properties "Micro Genetic Algorithm (mGA) Group Optimization Methods for Engineers" that made it in to search keywords. Attempt to correct this | 2 | |
17:47, 30 January 2014 | Block diagram of the LEG-CVA receiver.png (file) | 355 KB | Top: A block diagram of the LEG-CVA receiver. Bottom: Modem Bit-Error-Rate vs. Received Signal-to-Noise Power Ratio for TD-HSPA, Case-3 Multipath Channel, 16-CDMA codes and 64-QAM. | 1 | |
18:35, 28 January 2014 | Sandstorm layout.png (file) | 344 KB | 1 | ||
17:38, 29 January 2014 | Measured high resolution folding ADC.png (file) | 322 KB | Left: Measured output spectrum of a sinusoidal input signal at 60.123 MHz sampled at 150 MHz. Right: Chip micrograph of the implemented ADC in 130 nm CMOS. | 1 | |
16:29, 28 January 2014 | Graestl.png (file) | 304 KB | Top: FPGA floorplan containing the microprocessor and the GrÆStl cryptographic co-processor. Bottom: Photo of the manufactured Chameleon chip, hosting a separate AES/Grøstl design and GrÆStl. | 1 | |
18:32, 29 January 2014 | Block diagram of the space-time interference canceller.png (file) | 302 KB | Top: Interference scenario in cellular radio. Center: Layout of the RazorEDGE baseband ASIC Bottom: Block diagram of the space-time interference canceller. | 1 | |
10:10, 4 February 2014 | Channel Decoding for TD-HSPA.png (file) | 300 KB | Top: High-level architecture of the channel decoding chain for the downlink terminal side of 3GPP TD-HSPA. Bottom: Layout of the fabricated turbo and Viterbi decoder prototypes integrated in 180 nm CMOS technology. | 1 | |
17:10, 28 January 2014 | 3D board of qcrypt.png (file) | 278 KB | This picture shows a 3D model of the new version of the PCB. All network connections are now located on the top side of the board, making it suitable for dense housing in racks. | 1 | |
17:14, 13 November 2017 | Too lazy too busy.jpg (file) | 273 KB | I am too lazy to write anything on this page | 1 | |
20:48, 27 March 2014 | Hardware Accelerator for Model Predictive Controller1.png (file) | 238 KB | 1 | ||
17:46, 29 January 2014 | Baseband filter transfer functions.png (file) | 194 KB | Measured baseband filter transfer functions, demonstrating the flat transfer function and the wide range of programmability in terms of frequency and gain. | 1 | |
17:27, 30 January 2014 | Successive interference cancellation multi user detector.png (file) | 192 KB | Performance of the successive interference cancellation multi user detector (SIC-MUD) and the corresponding hardware implementation compared to the traditional linear MMSE equalizer. | 1 | |
17:21, 28 January 2014 | Serpent high throughput.png (file) | 190 KB | Block diagram illustrating the OCB-Serpent architecture with four fully-unrolled Serpent cores. | 1 | |
10:33, 4 February 2014 | Exploitation of Inherent Error Resilience of Wireless Systems.png (file) | 187 KB | Top: Simplified block diagram of the considered 3GPP TD-HSPA wireless communication system (receive side). Bottom: Throughput performance of the system including re-transmissions with hybrid-ARQ for various defect rates. | 1 | |
08:14, 7 November 2017 | Project map 2017 10.png (file) | 182 KB | 1 | ||
10:18, 4 February 2014 | Turbo Decoder Design for High Code Rates.png (file) | 181 KB | The impact of code rate on throughput and memory capacity of traditional acquisition-run-based turbo decoders (ATD) and state-metric-propagation-based turbo decoder implementations (STD). | 1 | |
17:14, 8 March 2014 | Simulation of novel solar cell architectures.png (file) | 169 KB | 1 | ||
17:04, 30 January 2014 | Setup of OsmoPHY together with RX board.png (file) | 153 KB | Top: Software architecture of the OsmoPHY framework. Bottom: Setup of OsmoPHY together with RX board, OsmocomBB and wireshark0 protocol analyzer. | 1 | |
17:07, 16 January 2014 | Channel Estimation of 3GPP.jpg (file) | 142 KB | 1 | ||
18:47, 7 July 2015 | Pulp block diag.png (file) | 137 KB | Block diagram of the PULP system | 1 | |
17:11, 30 January 2014 | High-level dedicated IR architecture storing punctured RLC blocks.png (file) | 135 KB | Top: Simulation results for coding schemes MCS-9 and DAS-12 in order to evalute IR performance. Bottom: High-level dedicated IR architecture storing punctured RLC blocks. | 1 | |
15:00, 16 January 2014 | Variation Tolerant.jpg (file) | 132 KB | 1 | ||
10:39, 4 February 2014 | Data Mapping for Unreliable Memories.png (file) | 130 KB | Top: Digital communication system employing BPSK transmission over an AWGN channel with unreliable memory. Bottom: Bit-error rate performance of the system assuming convolutional coding for different data representations. | 1 | |
17:01, 16 January 2014 | Multiuser Equalization and Detection.jpg (file) | 128 KB | 1 | ||
17:11, 16 January 2014 | Synchronization and Power Control Concepts.jpg (file) | 122 KB | 1 | ||
18:40, 10 May 2017 | Hyperdimensional EMG.png (file) | 121 KB | 1 | ||
18:41, 16 January 2014 | Creating Transmitter and Testbed Development for TD-SCDMA.jpg (file) | 121 KB | 1 | ||
17:28, 29 January 2014 | Simulated spectrum of high resolution large bw.png (file) | 121 KB | Simulated spectrum at the output of the modulator for a sinusoidal input signal at 40MHz. | 1 | |
18:49, 28 January 2014 | AMP OMP block diagram.png (file) | 118 KB | 2 | ||
09:02, 21 December 2017 | Qudev project.jpg (file) | 117 KB | 1 | ||
17:18, 8 March 2014 | Simulation of the optical properties of nanostructured solar cells.png (file) | 105 KB | 1 |
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