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Showing below up to 20 results in range #31 to #50.

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31. (hist) ‎Audio Visual Speech Recognition (1S/1M) ‎[9,414 bytes]
32. (hist) ‎Audio Visual Speech Separation (1S/1M) ‎[9,412 bytes]
33. (hist) ‎ISA extensions in the Snitch Processor for Signal Processing (M) ‎[9,151 bytes]
34. (hist) ‎Interfacing PULP with a Brain-Inspired Ultra-Low Power Spiking Cochlea ‎[9,139 bytes]
35. (hist) ‎Design and Implementation of a Convolutional Neural Network Accelerator ASIC ‎[9,080 bytes]
36. (hist) ‎On - Device Continual Learning for Seizure Detection on GAP9 ‎[9,053 bytes]
37. (hist) ‎Rethinking our Convolutional Network Accelerator Architecture ‎[9,007 bytes]
38. (hist) ‎Extreme-Edge Experience Replay for Keyword Spotting ‎[8,980 bytes]
39. (hist) ‎Heroino: Design of the next CORE-V Microcontroller ‎[8,937 bytes]
40. (hist) ‎Manycore System on FPGA (M/S/G) ‎[8,654 bytes]
41. (hist) ‎Continual Learning for Adaptive EEG Monitoring in Epileptic Seizure Detection ‎[8,413 bytes]
42. (hist) ‎MCU Bus and Memory Generator: implementation of a Highly Configurable bus and memory subsystem for a RISC-V based microcontroller. ‎[8,411 bytes]
43. (hist) ‎A Snitch-Based SoC on iCE40 FPGAs (1-2S/B) ‎[8,380 bytes]
44. (hist) ‎An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S) ‎[8,317 bytes]
45. (hist) ‎High-speed Scene Labeling on FPGA ‎[8,302 bytes]
46. (hist) ‎Design of Scalable Event-driven Neural-Recording Digital Interface ‎[8,231 bytes]
47. (hist) ‎A reduction-capable AXI XBAR for fast M-to-1 communication (1M) ‎[8,184 bytes]
48. (hist) ‎FFT-based Convolutional Network Accelerator ‎[8,120 bytes]
49. (hist) ‎Improved State Estimation on PULP-based Nano-UAVs ‎[8,098 bytes]
50. (hist) ‎Improving our Smart Camera System ‎[8,056 bytes]

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