Long pages

Showing below up to 20 results in range #41 to #60.

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41. (hist) ‎Continual Learning for Adaptive EEG Monitoring in Epileptic Seizure Detection ‎[8,413 bytes]
42. (hist) ‎MCU Bus and Memory Generator: implementation of a Highly Configurable bus and memory subsystem for a RISC-V based microcontroller. ‎[8,411 bytes]
43. (hist) ‎A Snitch-Based SoC on iCE40 FPGAs (1-2S/B) ‎[8,380 bytes]
44. (hist) ‎An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S) ‎[8,317 bytes]
45. (hist) ‎High-speed Scene Labeling on FPGA ‎[8,302 bytes]
46. (hist) ‎Design of Scalable Event-driven Neural-Recording Digital Interface ‎[8,231 bytes]
47. (hist) ‎A reduction-capable AXI XBAR for fast M-to-1 communication (1M) ‎[8,184 bytes]
48. (hist) ‎FFT-based Convolutional Network Accelerator ‎[8,120 bytes]
49. (hist) ‎Improved State Estimation on PULP-based Nano-UAVs ‎[8,098 bytes]
50. (hist) ‎Improving our Smart Camera System ‎[8,056 bytes]
51. (hist) ‎Peripheral Event Linking System for Real-time Capable Energy Efficient SoCs ‎[8,002 bytes]
52. (hist) ‎Practical Reconfigurable Intelligent Surfaces (RIS) ‎[7,979 bytes]
53. (hist) ‎Floating-Point Divide & Square Root Unit for Transprecision ‎[7,966 bytes]
54. (hist) ‎Spatz grows wings: Physical Implementation of a Vector-Powered Manycore System (2S) ‎[7,927 bytes]
55. (hist) ‎RISC-V based Implementation of Secure Ranging According to IEEE 802.15.4z UWB ‎[7,824 bytes]
56. (hist) ‎GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S) ‎[7,808 bytes]
57. (hist) ‎Mixed-Precision Neural Networks for Brain-Computer Interface Applications ‎[7,773 bytes]
58. (hist) ‎Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S) ‎[7,696 bytes]
59. (hist) ‎Self-Supervised User Positioning in Cell-Free Massive MIMO Systems ‎[7,691 bytes]
60. (hist) ‎Towards the Ariane Desktop: Display Output for Ariane on FPGA under Linux (S/B/G) ‎[7,663 bytes]

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