Search results

Create the page "System" on this wiki! See also the search results found.

Page title matches

• Category:Biomedical System on Chips
  #REDIRECT [[Biomedical System on Chips]]
  3 members (0 subcategories, 0 files) - 08:35, 7 November 2017
• System on Chips for IoTs
  48 bytes (8 words) - 11:25, 7 November 2017
• Biomedical System on Chips
  0 bytes (0 words) - 19:23, 23 November 2022
• Wake Up Radio For Energy Efficient Communication System and IC Design
  ...he student he can be involved on the design of the IC, the layout, or at a system and application levler. The wake-up receiver should achieves power consumpt ...classification accuracy and energy efficiency and to further optimize the system.
  5 KB (686 words) - 11:54, 2 February 2018
• A Waypoint-based Navigation System for Nano-Size UAVs in GPS-denied Environments
  4 KB (605 words) - 16:35, 20 February 2018
• Optimal System Duty Cycling for a Mobile Health Platform
  ...hanism both for sub-systems on the chip level as well as components on the system level, e.g. flash memory or radio ICs. This project focuses on chip-level d ...dictates battery size, the most critical factor in any volume-constrained system.
  4 KB (597 words) - 16:57, 12 July 2022
• Optimal System Duty Cycling
  0 bytes (0 words) - 14:44, 23 May 2018
• A Wearable Wireless Kidney Function Monitoring System For BioMedical Applications
  ..., non-invasive method to measure kidney performance via an external sensor system to avoid the use of urinary catheters for this subgroup of patients, thereb ...classification accuracy, and energy efficiency and to further optimize the system. The work includes the modeling and design of a suited impedance sensor, it
  6 KB (857 words) - 15:37, 10 November 2020
• Multisensory system for performance analysis in ski jumping (M/1-2S/B)
  ...roject focusses on the development of an unobtrusive multisensory embedded system to assist coaches to better quantify jumping trajectories of athletes. With ...perceptible to the athlete so as not to disturb his/her sensitive jumping system.
  6 KB (820 words) - 12:13, 23 July 2023
• PULP in space - Fault Tolerant PULP System for Critical Space Applications
  ...pikes due to cosmic rays being captured by sequential elements, taking the system into a faulty state.
  6 KB (980 words) - 14:46, 2 June 2021
• Fault Tolerant OpenPULP System for Critical Spacial Applications
  #REDIRECT [[PULP in space - Fault Tolerant PULP System for Critical Space Applications]]
  88 bytes (13 words) - 13:10, 9 August 2019
• Neuromorphic Intelligence In An Embedded System in Collaboration with AiCTX
  ...rphic intelligence using their processor to build a whole working embedded system. The student will deal with both hardware and software building a prototype * Motivation to build and test a real system
  5 KB (692 words) - 15:45, 10 November 2020
• High-throughput Embedded System For Neurotechnology in collaboration with INI
  ...ock diagram, which involves both the programming of a Low power FPGA and a System on Chip with ARM cortex-M4F and Bluetooth low energy 5.0. The project is qu * Motivation to build and test a real system
  4 KB (526 words) - 15:48, 10 November 2020
• Manycore System on FPGA (M/S/G)
  <!-- Manycore System on FPGA --> At ETH, we are developing our own many-core system called MemPool [1]. It boasts 256 lightweight 32-bit Snitch cores developed
  8 KB (1,319 words) - 10:41, 6 July 2021
• Implementation of a Heterogeneous System for Image Processing on an FPGA
  0 bytes (0 words) - 12:48, 2 November 2020
• (M): A Flexible Peripheral System for High-Performance Systems on Chip
  0 bytes (0 words) - 12:16, 2 November 2020
• Implementation of a Heterogeneous System for Image Processing on an FPGA (S)
  ...s is to have Halide programmed image processing kernels running on an HERO system implemented on an FPGA.
  5 KB (737 words) - 17:26, 2 November 2020
• A Flexible Peripheral System for High-Performance Systems on Chip (M)
  <!-- (M): A Flexible Peripheral System for High-Performance Systems on Chip --> One of the most tedious and error-prone steps is assembling a peripheral system with the required and desired IO; this usually involves adapting existing p
  11 KB (1,675 words) - 15:40, 15 March 2021
• Implementation of a Heterogeneous System for Image Processing on an FPGA (M)
  #REDIRECT [[Implementation of a Heterogeneous System for Image Processing on an FPGA (S)]]
  90 bytes (13 words) - 17:26, 2 November 2020
• Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)
  ...s private memory banks---this, however, impacts the programmability of the system. ...eved through a cache hierarchy, which impacts the energy efficiency of the system through its non-negligible power consumption.
  8 KB (1,196 words) - 10:41, 6 July 2021

Page text matches

• Reading The GSM Beacon Carrier with OsmocomBB and stoneEDGE
  The IIS 2G testbed has no operating system (OS) running on [4] FreeRTOS - Market leading RTOS (Real Time Operating System) for embedded systems
  3 KB (421 words) - 10:40, 6 November 2017
• Open Source Baseband Firmware for 2G Cellular Networks
  ...tp://www.freertos.org/ FreeRTOS - Market leading RTOS (Real Time Operating System) for embedded systems with Internet of Things extensions], June 2015.
  2 KB (273 words) - 11:30, 24 February 2017
• CPS Software-Configurable State-Machine
  ...data over a wireless link. Some of these system even include an actuation system, which reacts depending on the captured data. ...nnected and operate and act collaboratively it is called a 'cyper-physical system' (CPS).
  3 KB (418 words) - 11:24, 10 November 2017
• Design and Implementation of an Approximate Floating Point Unit
  ...tion of the FPUs and therefore reduce the overall power consumption of the system. Sharing FPUs allows to employ several different units, which can be either ...nd is a promising approach to further improve the energy efficiency of the system. One way to approximate FP-operations is to use Newton's method to compute
  3 KB (377 words) - 10:58, 21 February 2018
• Quantum Key Secured 100 Gbit/s Payload Encryption and its High-Speed Network Interfaces
  ...egory:Qcrypt|QCRYPT]] was the development of the 100 Gbit/s link encryptor system with a variety of optical interfaces on the plain-text side and a 100 Gbit ...main focus lay on the development of a second version of the PCB for this system. The layer stackup was modified to enhance the high-frequency quality of th
  2 KB (359 words) - 20:06, 17 February 2015
• High-Throughput Authenticated Encryption Architectures based on Block Ciphers
  ''2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC)'', Santa Cruz, California, USA, 7-10 Oct 2012
  3 KB (392 words) - 12:25, 26 March 2015
• Category:Qcrypt
  ...of quantum mechanics. However, existing systems are too slow. The new QKD system will be capable of producing keys at 1 Mbps rate, which means it will allow
  2 members (0 subcategories, 0 files) - 17:27, 28 January 2014
• Real-time View Synthesis using Image Domain Warping
  ...erent mobile platforms, most productions are captured with one acquisition system at fixed parameters. Examples for content adaption algorithms are content-a ...ons and VLSI Implementations", ''VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design, volume 418 of IFIP Advances in Information and Communicatio
  4 KB (520 words) - 16:04, 13 May 2015
• Feature Extraction with Binarized Descriptors: ASIC Implementation and FPGA Environment
  ...IC/FPGA system which implements the first three steps of this process. Our system is able to extract SKB features from one 720p video stream in real time (30
  3 KB (487 words) - 15:57, 13 May 2015
• Pirmin Vogel
  ...ing and embedded heterogeneous systems on a chip with a focus on operating system, driver, runtime and programming model support for efficient and transparen
  1 KB (193 words) - 15:39, 3 March 2020
• Image Sensor Interface and Pre-processing
  ...the image is being acquired and forward this information to a larger host system for further processing. ...algorithm steps directly ion hardware and interface with the host computer system.
  3 KB (357 words) - 18:53, 6 December 2014
• High-Resolution Large-Bandwidth Delta-Sigma A/D Converters in Ultra-Scaled CMOS
  ...bits. Such data converters are intended to be embedded in a mostly digital system, and this legitimates the adoption of ultra-scaled CMOS technologies from w
  2 KB (277 words) - 17:28, 29 January 2014
• Category:Placitus
  ...ying downscaling of CMOS technology to the nano scale device size and tera system complexity. This aggressive downscaling has allowed the number of transisto ...stem functionality into digital, analog and RF or sensor realizations on a system on chip optimally is one of the key topics that will impact the era of nano
  7 members (0 subcategories, 2 files) - 17:31, 29 January 2014
• Category:I-IronIC
  ==Implantable/Wearable System for on-line Monitoring of Human Metabolic Conditions== ...surements, while at the same time reducing analysis time and cost. The new system will investigate many different metabolic compounds of interest in cardiova
  1 member (0 subcategories, 0 files) - 18:14, 29 January 2014
• Wireless Biomedical Signal Acquisition Device
  Although the wireless and battery-powered nature of this system reduces the impact of mains interference, its amplitude might nonetheless b ...ed by an off-the-shelf mobile phone battery which is sufficient to run the system for several hours - the battery life-time is mainly limited by the Bluetoot
  2 KB (280 words) - 10:54, 10 March 2015
• Benjamin Weber
  his PhD thesis entitled "An Evolved EDGE System on Chip for the Cellular
  894 bytes (115 words) - 17:17, 30 November 2021
• Digitally-Controlled Analog Subtractive Sound Synthesis
  [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]
  5 KB (597 words) - 12:56, 4 December 2021
• MatPHY: An Open-Source Physical Layer Development Framework
  ...upper layers of the OsmocomBB GSM protocol stack. The functionality of the system is verified with a testbed comprising a base station and a receiver board w
  3 KB (360 words) - 14:14, 27 May 2015
• Evolved EDGE Physical Layer Incremental Redundancy Architecture
  ...ssor and the unit where RLC blocks are processed for IR is attached to the system processor. The decoding of the RLC blocks takes place on a PHY Digital Sign
  3 KB (397 words) - 14:12, 27 May 2015
• A Novel Constrained-Viterbi Algorithm with Linear Equalization and Grouping Assistance
  ...ons such as those in the time-duplexing high speed packet access (TD-HSPA) system.
  2 KB (266 words) - 10:43, 9 February 2015

View (previous 20 | next 20) (20 | 50 | 100 | 250 | 500)