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• Real-Time Pedestrian Detection For Privacy Enhancement
  : 20% Software Development, 60% FPGA Development & Verification : or 80% software development
  3 KB (408 words) - 13:17, 5 February 2016
• Physical Layer Implementation of HSPA+ 4G Mobile Transceiver
  ...der to facilitate a cost-effective network upgrade that is based solely on software upgrade without the need for replacing the operator's network equipment. ...tionality of a standard-compliant physical layer of a mobile communication system. Possibly, the student can also investigate and analyze an interesting perf
  1 KB (159 words) - 11:16, 23 September 2016
• Digital Transmitter for Cellular IoT
  ...the first EC-GSM capable transmitter implementation worldwide (except for software defined prototypes). [1] ''Cellular system support for ultra-low complexity and low throughput Internet of Things (CIo
  3 KB (384 words) - 16:41, 17 July 2016
• Real-Time Optical Flow Using Neural Networks
  [[Category:Digital]] [[Category:Software]] [[Category:Completed]] [[Category:Semester Thesis]] [[Category:Lukasc]] [ [[Category:Digital]] [[Category:System Design]]
  5 KB (707 words) - 11:22, 5 February 2016
• PULPonFPGA: Lightweight Virtual Memory Support - Software Cache
  ...erogeneous uniform memory access (hUMA) as envisioned by the Heterogeneous System Architecture (HSA) foundation, their low-power counterparts targeting the e ...L1 scratchpad memory, and the shared main memory to optimally exploit the system's memory hierarchy and to achieve high performance.
  5 KB (716 words) - 13:43, 29 November 2019
• High-speed Scene Labeling on FPGA
  ...an ethernet adapter. As opposed to an ASIC project, such FPGA and hardware-software codesign work is much more applicable in industry and less constrained in t ...to programmable logic and design an entire hetergeneous system using with software, FPGA fabric and hardwired interfaces.
  8 KB (1,197 words) - 18:18, 29 August 2016
• PULPonFPGA: Lightweight Virtual Memory Support - Coherency Extensions
  ...erogeneous uniform memory access (hUMA) as envisioned by the Heterogeneous System Architecture (HSA) foundation, their low-power counterparts targeting the e ...ators into embedded heterogeneous SoCs. We have developed a mixed hardware/software solution to enable lightweight virtual memory support for many-core acceler
  4 KB (585 words) - 17:57, 7 November 2017
• PULPonFPGA: Lightweight Virtual Memory Support - Multi-Level TLB
  ...erogeneous uniform memory access (hUMA) as envisioned by the Heterogeneous System Architecture (HSA) foundation, their low-power counterparts targeting the e ...ators into embedded heterogeneous SoCs. We have developed a mixed hardware/software solution to enable lightweight virtual memory support for many-core acceler
  4 KB (554 words) - 17:57, 7 November 2017
• Autonomous Sensing For Trains In The IoT Era
  ...ther important results will be provided by the combination of hardware and software co-design to achieve the ambitious goal of placing the smart sensor never r ...classification accuracy and energy efficiency and to further optimize the system.
  6 KB (774 words) - 08:36, 23 November 2022
• Switched Capacitor Based Bandgap-Reference
  [[Category:System Design]] [[Category:System Design]]
  4 KB (471 words) - 11:13, 3 May 2018
• Autonomous Smart Watches: Hardware and Software Desing
  ...classification accuracy and energy efficiency and to further optimize the system. : Interest in Computer Architectures at system level
  3 KB (448 words) - 11:59, 28 July 2015
• Improving our Smart Camera System
  ...hose in our prototype, and otherwise improve it by building a more compact system, adding communication capabilities to transmit suspicious cases to a remote [[Category:Digital]] [[Category:System]] [[Category:Semester Thesis]] [[Category:Group Work]]
  8 KB (1,176 words) - 16:26, 30 October 2020
• Efficient Implementation of an Active-Set QP Solver for FPGAs
  ...essing system on the Xilinx Zynq platform, and establish the corresponding software interface. : Matlab, C++, VHDL or System Verilog
  4 KB (542 words) - 12:39, 1 June 2017
• Development of a Rockfall Sensor Node
  ...ill be performed, with the main goal to develop the complete data-grabbing software and perform real-world tests in collaboration with SLF Davos. [[Category:System Design]]
  2 KB (340 words) - 11:55, 21 August 2018
• FPGA System Design for Computer Vision with Convolutional Neural Networks
  [[File:origami-fpga-system.png|400px|thumb]] ...o finish the processing pipeline (activation, pooling), and completing the system by connecting a camera or loading a video stream and displaying the results
  3 KB (397 words) - 18:17, 29 August 2016
• Learning Image Decompression with Convolutional Networks
  <!--[[File:origami-fpga-system.png|400px|thumb]] --> ...emester Thesis]] [[Category:Master Thesis]] [[Category:Lukasc]] [[Category:Software]] [[Category:2016]]
  2 KB (285 words) - 18:16, 29 August 2016
• Change-based Evaluation of Convolutional Neural Networks
  [[Category:Software]] [[Category:System]] [[Category:Completed]] [[Category:Semester Thesis]] [[Category:2016]] * Interest in computer vision and system engineering
  5 KB (747 words) - 18:04, 29 August 2016
• Using Motion Sensors to Support Indoor Localization
  • Experience in software engineering for embedded systems [[Category:System Design]]
  3 KB (426 words) - 11:41, 21 July 2017
• Turbo Equalization for Cellular IoT
  ...wn approach to improve the overall performance of a wireless communication system. The underlying principle is to feed back soft information from the channel [[Category:System Design]]
  3 KB (450 words) - 11:43, 13 November 2018
• PULPonFPGA: Hardware L2 Cache
  ...w evaluation platform based on the Juno ARM Development Platform [3]. This system combines a modern ARMv8 multicluster CPU with a Xilinx Virtex-7 XC7V2000T F : VHDL/System Verilog, C
  5 KB (711 words) - 10:27, 5 November 2019

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