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  • Template
    : 40% ASIC Design * '''[[Design Review]]'''
    4 KB (397 words) - 15:44, 14 February 2023
  • High Performance Cellular Receivers in Very Advanced CMOS
    ...t, that all digital parts following the analog-to-digital converter of the RF receiver baseband part. On the other side drawbacks for analog circuits als
    2 KB (275 words) - 13:02, 10 March 2015
  • Indoor Positioning with Bluetooth
    ...he position of the IoT device. This baseband can then be integrated on our RF SoC. : 50% Hardware design (HLS or VHDL)
    3 KB (449 words) - 12:12, 4 November 2019
  • Advanced 5G Repetition Combining
    ...u can either design an ASIC with only this block, or integrate it into our RF SoC and test it on an FPGA. : 40% Hardware Design (HLS/VHDL)
    3 KB (345 words) - 10:52, 5 April 2022
  • OpenRISC SoC for Sensor Applications
    ...ion of the OpenRisc was completed as part of a [[Ultra-low power processor design | previous semester thesis]]. We are already using this core in our [[:Cate ...uires the attention of the processor. The wake-up radio will listen to the RF interface and will detect if there is a radio transmission addressing the c
    4 KB (667 words) - 15:23, 23 December 2016
  • Analog
    = Analog and Mixed Signal Design Group = The Analog and Mixed Signal Design Group is specialized in designing mixed signal integrated circuits and syst
    3 KB (369 words) - 18:11, 1 March 2023
  • Ambient RF Energy harvesting for Wireless Sensor Network
    ...n be used to extend the battery life time such as Solar, Thermal, Kinetic, RF. ...will demonstrate that Radio Frequency energy can always be harvested. The RF harvested will be interfaced with also with a nano power wake up radio and
    3 KB (378 words) - 19:56, 9 February 2015
  • Digital Transmitter for Cellular IoT
    ...jpg|thumb|2G Testbed setup with L2/L3 processing on ZedBoard (top), double RF on evalEDGE v1.0 (middle), and baseband on ML605 (bottom).]] ...otyping. This project will involve modeling in Matlab but mostly it is HDL design, synthesis, and FPGA testing.
    3 KB (384 words) - 16:41, 17 July 2016
  • Gomeza old project2
    ...olar panel for energy harvesting. The main objective of this project is to design a new version of the sensor node with the added functionality of a nano-pow
    3 KB (376 words) - 18:04, 28 January 2017
  • Baseband Processor Development for 4G IoT
    [[File:4G_soc.png|thumb|4G modem SoC with RF, DBB, and L2/L3.]] ...jpg|thumb|2G Testbed setup with L2/L3 processing on ZedBoard (top), double RF on evalEDGE v1.0 (middle), and baseband on ML605 (bottom).]]
    2 KB (347 words) - 17:58, 14 April 2016
  • Beat DigRF
    ...[2]. However, the DigRF standard is by definition the interface between an RF IC and a DBB IC. Hence, it is an off-chip interface and by no means intende ...nts. This project provides a good opportunity to dig deep into an existing design and hopefully give reason to refrain from using off-chip interfaces for on-
    2 KB (299 words) - 17:58, 14 April 2016
  • Internet of Things Network Synchronizer
    ...he [[stoneEDGE]] project and the [[evalEDGE]] RF board. Synthesis and ASIC design are also an option.
    4 KB (582 words) - 20:00, 26 September 2017
  • Using Motion Sensors to Support Indoor Localization
    ...on of moving targets can be achieved with different technologies including RF, * '''[[Design Review]]'''
    3 KB (426 words) - 11:41, 21 July 2017
  • Implementation of a NB-IoT Positioning System
    ...NB-IoT-baseband implementation. This step includes a hardware-software co-design in which part of the algorithm will be mapped onto a PULP processor while c : 40% Hardware/Software Co-Design (Programming in HDL and C)
    4 KB (555 words) - 16:36, 23 May 2018
  • WCDMA/HSPA+ Synchronization System Design, Implementation, and Testing
    ...processing on [[PULP]] as well as dedicated DBB processing on an FPGA and RF on [[evaLTE]] FMC module. ...eloped modem is mapped to a Kintex 7 FPGA in conjunction with a commercial RF from ACP AG.
    2 KB (340 words) - 10:39, 6 November 2017
  • Passive and Self Sustaining Receivers For On and Intra Body Communication For Wearable Sensors Networks
    ...project will also focus on how make the whole system self-sustaining using RF energy harvesting or other kind of energy harvesting suitable the the speci ...e existing prototype: verification of the prototype's characteristics w.r. design specification (simulations), measuring power-consumption, and assessing det
    4 KB (576 words) - 16:58, 28 July 2017
  • Radio Signal Direction Detection For Smart Glasses For Augmented Reality Applications
    The student will design and implement an ultra low power system testing the performances of the whole system by using a commercial RF
    4 KB (609 words) - 11:38, 21 July 2017
  • FPGA-based Testbed Implementation of an Extended-Coverage Point-to-Point Communication Link for the Internet of Things
    [[Category:System Design]]
    3 KB (462 words) - 13:54, 13 November 2020
  • LTE IoT Network Synchronization
    : 40% Hardware/Software Co-Design (C, HLS/VHDL) [[RF SoCs for the Internet of Things]]
    3 KB (440 words) - 16:32, 18 May 2018
  • IoT Turbo Decoder
    [[File:High Throughput Turbo Decoder Design.png|400px|thumb|A previous, high throughput, Turbo Decoder developed at IIS ...ce the area is the sharing of memory with the processor cluster. The final design can either be mapped to an FPGA, or an ASIC.
    3 KB (427 words) - 09:37, 14 September 2018

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