Difference between revisions of "User:Sarjmandpour"
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==Interests== | ==Interests== | ||
| − | My research focuses on Analog/ Mixed signal circuit design, specifically in All digital PLLs and SERDES circuits. My current | + | My research focuses on Analog/ Mixed signal circuit design, specifically in All digital PLLs and SERDES circuits. My current research is designing low-power wireline transceivers for IOT applications. I previously designed both analog and All digital PLL as well. |
==Contact Information== | ==Contact Information== | ||
Latest revision as of 13:00, 13 February 2023
Sina Arjmandpour
Interests
My research focuses on Analog/ Mixed signal circuit design, specifically in All digital PLLs and SERDES circuits. My current research is designing low-power wireline transceivers for IOT applications. I previously designed both analog and All digital PLL as well.
Contact Information
- Office: ETZ J88
- e-mail: sarjmandpour@iis.ee.ethz.ch
- phone: +41 44 632 82 21
- www: IIS Homepage
