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Configurable Ultra Low Power LDO

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Status: Available

Looking for master or semester thesis students


The project aims to design an ultra-low-power Low Dropout Regulator (LDO) to control the impedance in a voltage-mode driver. The LDO will provide a stable output voltage with a high level of accuracy while consuming minimal power. The design will be optimized for low quiescent current and low dropout voltage to achieve maximum efficiency. The LDO will be integrated into the voltage-mode driver circuit to regulate the output impedance and improve the performance of the driver. The project will involve circuit design, simulation, and layout using industry-standard CAD tools. The final design will be fabricated and tested to verify the performance of the ultra-low-power LDO.


  • Analog integrated circuit design course
  • Energy-Efficient Analog Circuits for IoT Systems is a plus


  • 30% Theory
  • 30% Simulation
  • 40% Circuit design


  • Prof. Dr. Taekwang Jang

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