User:Cykoenig
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Cyril Koenig
Benchmarking_a_RISC-V-based_Accelerator_Cards_for_Inference_(SA)
Contact
- e-mail: cykoenig@iis.ee.ethz.ch
- office: ETZ J76.2
Research
Projects
Available Projects
- Extending the HERO SDK to support asynchronous offloading (M/1-3S)
- Benchmarking RISC-V-based Accelerator Cards for Inference (multiple SA)
- Benchmarking a RISC-V-based Server on LLMs/Foundation Models (SA or MA)
- Extending the HERO RISC-V HPC stack to support multiple devices on heterogeneous SoCs (M/1-3S)
- Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
Projects In Progress
- Writing a Hero runtime for EPAC (1-3S/B)
- Building an RTL top level for a Mempool-based Heterogeneous SoC (M/1-3S)
Completed Projects
- Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
- A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B)
Archived
