Implementation of an AES Hardware Processing Engine (B/S)
From iis-projects
Introduction
The Advanced Encryption Standard (AES) [1] is an encryption algorithm used in many of today's applications. It operates in multiple rounds on fixed-size data blocks, converting a clear-text data stream into an encrypted one (or vice-versa). This process is computationally expensive, and can become a bottleneck when applied on large amounts of data. A solution to this problem is a dedicated hardware accelerator that directly operates on the data that should be en-/decrypted.
Project
This project proposes to implement an AES accelerator for the PULP platform [2], interfacing as a Hardware Processing Engine (HWPE) [3] and operating directly on the Tightly-Coupled Data Memory (TCDM), to serve as a baseline for future follow-up work, and to provide an open-source reference implementation that is compatible with PULP. The main components of this thesis are:
- RTL-implementation of the AES HWPE,
- Validation the design using existing reference implementations,
- Performing a basic design-space exploration of the accelerator.
Depending on the progress, the component can furthermore be integrated into PULPissimo [4], and prepared for a tape-out.
Requirements
- Strong interest in hardware design
- Experience with HDLs (preferably SystemVerilog) such as taught in VLSI I
- Knowledge of ASIC tool flow (Synthesis) or parallel enrollment with VLSI II is beneficial
Composition: 25% Design specification, 25% RTL Implementation, 25% Verification, 25% Synthesis and design-space exploration
