Category:Bachelor Thesis

Available Projects

• Resource Partitioning of RPC DRAM
• Vector-based Parallel Programming Optimization of Communication Algorithm (1-2S/B)
• Finalizing and Releasing Our Open-source AXI4 IPs (1-3S/B/2-3G)
• Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B)
• Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B)
• Smart Meters
• Creating a Compact Power Supply and Monitoring System for the Occamy Chip (1-3S/B/2-3G)
• Design and Implementation of a Fully-digital Platform-independent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B)
• Towards a High-performance Open-source Verification Suite for AXI-based Systems (M/1-3S/B)
• Big Data Analytics Benchmarks for Ara
• All the flavours of FFT on MemPool (1-2S/B)
• Virtual Memory Ara
• Runtime partitioning of L1 memory in Mempool (1-2S/B)
• Extended Verification for Ara
• A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B)
• Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B)
• Integration Of A Smart Vision System
• Towards Formal Verification of the iDMA Engine (1-3S/B)
• Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B)
• Wearable Ultrasound for Artery monitoring
• New RVV 1.0 Vector Instructions for Ara
• Smart e-glasses for concealed recording of EEG signals
• Enhancing our DMA Engine with Fault Tolerance
• Analog building blocks for mmWave manipulation
• A mmWave Voltage-Controlled-Oscillator (VCO) for beyond 5G applications
• Bluetooth Low Energy network with optimized data throughput
• Design of Time-Encoded Spiking Neural Networks (IBM-Zurich)
• Ternary Neural Networks for Face Recognition
• Bluetooth Low Energy receiver in 65nm CMOS
• RVfplib
• Charge-Pump PLL with ring-oscillator based VCO in 65nm CMOS
• Bandgap voltage reference in 65nm CMOS
• IP-Based SoC Generation and Configuration (1-3S/B)

Active Projects

• Extension and Evaluation of TinyDMA (1-2S/B/2-3G)
• Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B)
• Event-Driven Vision on an embedded platform
• ASIC Development of 5G-NR LDPC Decoder

Completed Projects

• Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B)
• Adding Linux Support to our DMA Engine (1-2S/B)
• Watchdog Timer for PULP
• Next Generation Synchronization Signals
• Implementation of an AES Hardware Processing Engine (B/S)
• Low-Dropout Regulators for Magnetic Resonance Imaging
• DC-DC Buck converter in 65nm CMOS
• Towards the Ariane Desktop: Display Output for Ariane on FPGA under Linux (S/B/G)
• Ottocore: A Minimal RISC-V Core Designed for Teaching (B/2G)
• A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)
• Manycore System on FPGA (M/S/G)