Category:Bachelor Thesis
From iis-projects
Available Projects
- Advanced Data Movers for Modern Neural Networks
- Creating an At-memory Low-overhead Bufferless Matrix Transposition Accelerator (1-3S/B)
- Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1-3S/B)
- A RISC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks (1-2S/B)
- Advanced Physical Design: Reinforcement Learning for Macro Placement and Mix-Placer (B/1-2S)
- Vector-based Parallel Programming Optimization of Communication Algorithm (1-2S/B)
- EEG-based drowsiness detection
- In-ear EEG signal acquisition
- EEG earbud
- Designing a Scalable Miniature I/O DMA (1-2B/1-3S/M)
- Reliability by Switching the Embedded ISA in Ibex (1-2S/B/1M)
- RedCap-5G for IOT application on prototype taped-out silicon
- Advanced EEG glasses
- Testbed Design for Self-sustainable IoT Sensors
- Towards Flexible and Printable Wearables
- Modular Distributed Data Collection Platform
- On-Board Software for PULP on a Satellite
- Digital Control of a DC/DC Buck Converter
- Resource Partitioning of RPC DRAM
- Finalizing and Releasing Our Open-source AXI4 IPs (1-3S/B/2-3G)
- Design and Implementation of a Fully-digital Platform-independent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B)
- Towards a High-performance Open-source Verification Suite for AXI-based Systems (M/1-3S/B)
- All the flavours of FFT on MemPool (1-2S/B)
- Extended Verification for Ara
- Integration Of A Smart Vision System
- Towards Formal Verification of the iDMA Engine (1-3S/B)
- Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B)
- Wearable Ultrasound for Artery monitoring
- Enhancing our DMA Engine with Fault Tolerance
- Analog building blocks for mmWave manipulation
- A mmWave Voltage-Controlled-Oscillator (VCO) for beyond 5G applications
- Bluetooth Low Energy network with optimized data throughput
- Design of Time-Encoded Spiking Neural Networks (IBM-Zurich)
- RVfplib
- IP-Based SoC Generation and Configuration (1-3S/B)
Active Projects
- Low Precision Ara for ML
- New RVV 1.0 Vector Instructions for Ara
- Big Data Analytics Benchmarks for Ara
- Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B)
- Ternary Neural Networks for Face Recognition
- Event-Driven Vision on an embedded platform
- ASIC Development of 5G-NR LDPC Decoder
Completed Projects
- Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B)
- Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B)
- Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B)
- Extension and Evaluation of TinyDMA (1-2S/B/2-3G)
- Creating a Compact Power Supply and Monitoring System for the Occamy Chip (1-3S/B/2-3G)
- A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B)
- Smart e-glasses for concealed recording of EEG signals
- Smart Meters
- Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B)
- Running Rust on PULP
- Bluetooth Low Energy receiver in 65nm CMOS
- Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B)
- Adding Linux Support to our DMA Engine (1-2S/B)
- Watchdog Timer for PULP
- Next Generation Synchronization Signals
- Implementation of an AES Hardware Processing Engine (B/S)
- Low-Dropout Regulators for Magnetic Resonance Imaging
- DC-DC Buck converter in 65nm CMOS
- Towards the Ariane Desktop: Display Output for Ariane on FPGA under Linux (S/B/G)
- Ottocore: A Minimal RISC-V Core Designed for Teaching (B/2G)
- A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)
- Manycore System on FPGA (M/S/G)
Pages in category "Bachelor Thesis"
The following 69 pages are in this category, out of 69 total.
A
- A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B)
- A mmWave Voltage-Controlled-Oscillator (VCO) for beyond 5G applications
- A RISC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks (1-2S/B)
- A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)
- Adding Linux Support to our DMA Engine (1-2S/B)
- Advanced Data Movers for Modern Neural Networks
- Advanced EEG glasses
- Advanced Physical Design: Reinforcement Learning for Macro Placement and Mix-Placer (B/1-2S)
- All the flavours of FFT on MemPool (1-2S/B)
- Analog building blocks for mmWave manipulation
- ASIC Development of 5G-NR LDPC Decoder
B
C
- Combining Multi Sensor Imaging and Machine Learning for Robust Far-Field Vision
- Creating A Boundry Scan Generator (1-3S/B/2-3G)
- Creating a Compact Power Supply and Monitoring System for the Occamy Chip (1-3S/B/2-3G)
- Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B)
- Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B)
- Creating an At-memory Low-overhead Bufferless Matrix Transposition Accelerator (1-3S/B)
D
- DC-DC Buck converter in 65nm CMOS
- Design and Implementation of a Fully-digital Platform-independent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B)
- Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1-3S/B)
- Design of Time-Encoded Spiking Neural Networks (IBM-Zurich)
- Designing a Scalable Miniature I/O DMA (1-2B/1-3S/M)
- Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B)
- Digital Control of a DC/DC Buck Converter
E
- EEG earbud
- EEG-based drowsiness detection
- Enhancing our DMA Engine with Fault Tolerance
- Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B)
- Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B)
- Evaluating An Ultra low Power Vision Node
- Event-Driven Vision on an embedded platform
- Extended Verification for Ara
- Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B)
- Extension and Evaluation of TinyDMA (1-2S/B/2-3G)
I
- Implementation of an AES Hardware Processing Engine (B/S)
- Implementing A Low-Power Sensor Node Network
- Improved Reacquisition for the 5G Cellular IoT
- Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B)
- In-ear EEG signal acquisition
- Integration Of A Smart Vision System
- IP-Based SoC Generation and Configuration (1-3S/B)
O
R
T
- Ternary Neural Networks for Face Recognition
- Testbed Design for Self-sustainable IoT Sensors
- Towards a High-performance Open-source Verification Suite for AXI-based Systems (M/1-3S/B)
- Towards Flexible and Printable Wearables
- Towards Formal Verification of the iDMA Engine (1-3S/B)
- Towards the Ariane Desktop: Display Output for Ariane on FPGA under Linux (S/B/G)
