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Design of Time-Encoded Spiking Neural Networks (IBM-Zurich)

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Powerful models that rely on artificial neural networks (ANNs) have acquired wide popularity in the last decade. Spiking neural networks (SNNs) represent a very efficient class of neural networks, which communicate through sequences of spikes, thus closely resembling biological neural networks. The spike trains are commonly interpreted as all-or-none signals, corresponding to binary communication with ones and zeros, in which spikes (ones) are sparse and asynchronous, leading to efficient operation.

Neural encoding deals with determining how information is communicated by electrical signals (action potentials) at the level of individual neurons in SNNs. Fast processing of information is achieved by time encoding methods, where neural communication is based on the precise timing of action potentials, as for example Time-to-First-Spike (TTFS) encoding, where a neuron spikes once when its membrane potential reaches a given threshold, and afterwards it remains silent. TTFS encoding is well suited for low-latency classification algorithms, where the neuron corresponding to the correct class fires first among the top layer neurons.

We are inviting students to conduct their thesis work (master or bachelor) at IBM Research – Zurich on this exciting topic. The work performed could span hardware design at the circuit level of time-encoded SNNs to high-level system simulations in a high-performance computing framework. It also involves interactions with several researchers across IBM Research focusing on various aspects of the project.

Status: Available

Looking for master or bachelor thesis students

If you are interested in this challenging position on an exciting and challenging topic, please send your most recent curriculum vitae including a transcript of grades by email to:

Dr. Angeliki Pantazi <>


The ideal candidate should have a multi-disciplinary background, strong mathematical aptitude and programming and circuit design skills (analog design on transistor level and/or digital design with VHDL). Prior knowledge of neuromorphic computing concepts is a bonus but not necessary.


Prof. Taekwang Jang <>

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