Creating A Boundry Scan Generator (1-3S/B/2-3G)

Overview

Status: Available

• Type: ASIC Bachelor / Semester Thesis or Group Project
• Professor: Prof. Dr. L. Benini
• Supervisors:
  • Thomas Benz: tbenz@iis.ee.ethz.ch

Introduction

When testing more complex ASICs in intricate packages, the JTAG boundary scan becomes a valuable tool to debug connectivity issues. Unfortunately, we currently have no way to generate the simple hardware required to implement the boundary scan in an arbitrary ASIC.

Project

You will create a tool that generates and inserts the required hardware around an existing ASIC design. Your generator should also create a testbench and the patterns for our ASIC tester to facilitate both verification and the actual testing of your boundary hardware.

Character

• 20% Study JTAG standard
• 40% Design, implementation, and verification of the generator
• 40% Implement your boundary scan hardware in an existing ASIC (and retape it)

Prerequisites

• Interest in memory systems
• Experience with digital design in SystemVerilog as taught in VLSI I
• Preferred: Visited VLSI II or an equivalent lecture