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Finalizing and Releasing Our Open-source AXI4 IPs (1-3S/B/2-3G)

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Status: Available


At IIS we are developing THE free and open-source AXI4 (Advanced eXtensible Interface) IP suite ( Our implementation is now almost at the point of reaching maturity. However, there are still some crucial key items missing before we can release our suite:

  • We lack core IPs (e.g. AXI Lite Data Width converter, the AXI4 reorder buffer (ROB), ...)
  • Protocol checkers (using SystemVerilog Assertions and Assume statements) are missing
  • We need a fully open-source CI (synthesis using Yosys, implementation using OpenRoad, simulation using Verilator/iverilog)
  • The IPs and the repository need to be homogenized (parameter names, interfaces, ...)


In this project, you have the rare opportunity to go all in with AXI4-based interconnect IPs. You will develop and verify important AXI-based IPs, create an open-source fully-turnkey ASIC implementation flow to track non-functional figures of merit in CI, and you will have the chance to contribute to a project that is used all over the world in a multitude of designs.


  • 20% Study the AXI4 spec, look at our IPs, and get familiar with our design philosophy
  • 30% Create and verify missing IPs, verify existing IPs with missing test benches, and improve coverage and speed of existing TBs
  • 20% Create a fully open-source CI
  • 30% Homogenoze all IPs


  • Interest in memory systems
  • Experience with digital design in SystemVerilog as taught in VLSI I
  • Preferred: Knowledge of AXI4