Floating-Point (FP) numbers are pervasive in the world of algorithms, thanks to their improved dynamic range and precision with respect to fixed-point and integer representations.
Today's processors that are supposed to operate on FP numbers can execute FP operations in two different ways.
- In hardware, exploiting a dedicated Floating-Point Unit (FPU). This means that the processor uses a circuit that was specifically designed to compute FP operations. This approach provides the best performance and computation efficiency, but it costs precious area and consumes energy if it is not used.
- In software, emulating each FP operation with a specific function that uses only integer numbers. The processor executes this function on the FP input numbers, and, after many integer instructions, it composes the FP result. This approach is slower if compared with FPU, but it does not require any hardware-specific circuit. On the other hand, the functions occupy precious memory space, and reducing the code size of the functions is an urgent priority.
When the circuit area is a constraint, or when the processor needs FP computations only sparingly, the second approach is the best choice; nevertheless, the performance, code size, and efficiency of the FP computation are strongly affected by the quality of the emulation functions.
Compiler vendors and individuals create optimized FP libraries, usually in assembly, to achieve the best performance possible. Since RISC-V lacked such optimized support, we created RVfplib, the first open-source FP-emulation library optimized in assembly for reduced code-size and improved performance (and efficiency).
RVfplib is a library that provides all the major arithmetic functions, comparison, and conversions between FP numbers. The library is at its first release and can be further optimized and extended with additional functions.
Project: Optimize and extend RVfplib
The goal of the project is to optimize and extend RVfplib.
- After a comparison with emFloat, a commercial optimized FP library , it was clear that the RVfplib division can be further optimized both in code size and performance.
- RVfplib does not yet provide the square root and the trigonometric functions.
Flow of the project.
- Research to become familiar with the topic.
- Optimization of the FP division for 32-bit and 64-bit
- Definition of the instructions to add, choice of the algorithms.
- Implementation of the instructions.
- Verification of the instructions.
- Evaluation of the instructions in terms of performance and code size.
- Strong interest in computer architecture
- Basic knowledge of floating-point computation
- Basic knowledge of the RISC-V ISA
- Basic knowledge of GCC toolchain is a plus
- Basic knowledge of digital hardware (VLSI I) is a plus
Composition: 20% Research, 30% Implementation, 25% Verification, 25% Evaluation (Benchmarking)
What will you learn
During the project, you will develop several skills.
- Use and understand the GCC compiler.
- Know how to use the RV32IM RISC-V assembly instructions.
- Know how to write optimized programs in RISC-V assembly.
- Know IEEE 754 Standard for Floating-Point Arithmetic.
- Know how to use SPIKE simulator for RISC-V.
- Know how to benchmark applications in terms of performance and code size.