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- ...or to easily create such architectures. This project requires knowledge of digital logic and VLSI implementation. : 50% VLSI Design5 KB (653 words) - 11:08, 12 November 2020
- ...i, T. Goldstein, and C. Studer, "Finite-Alphabet MMSE Equalization for All-Digital Massive MU-MIMO mmWave Communication," IEEE Journal on Selected Areas in Co * '''[[Design Review]]'''6 KB (829 words) - 11:37, 12 November 2020
- * '''[[Design Review]]''' [[Category:Digital]]6 KB (748 words) - 13:57, 12 November 2020
- ...sing HDL. The developed HDL code will be synthesized and implemented as an ASIC after placement and routing. The breakdown of the tasks will be as follows: * Placement and routing of the synthesized design3 KB (389 words) - 01:43, 10 February 2021
- * 20% FPGA RTL design * RTL Design in SystemVerilog and Xilinx FPGA flow as taught in VLSI I11 KB (1,602 words) - 15:19, 9 July 2021
- [[Category:Digital]] [[Category:FPGA]]8 KB (1,220 words) - 15:18, 9 July 2021
- ...a 32-bit in-order RISC-V core implementing the RV32IC instruction set. Its design is of high-quality, open source and it comes with an industry-grade verific ...eed you to bring into the project is basic knowledge in integrated circuit design (VLIS I/II lectures), team working skills, self-motivation, drive and a pos6 KB (835 words) - 12:52, 27 April 2021
- * '''[[Design Review]]''' [[Category:Digital]]6 KB (687 words) - 13:32, 10 May 2023
- * Knowledge of digital arithmetic (e.g., two's complement, overflow, wraparound) [[Category:Digital]]5 KB (659 words) - 14:08, 15 February 2024
- ...s logic has blatant advantages over synchronous designs, asynchronous VLSI design was, up until now, not supported by EDA tools and, hence, enjoyed only limi ...ls available at [2]. Third, the student(s) will compare their asynchronous design to state-of-the-art synchronous LDPC decoders in the same process technolog6 KB (725 words) - 17:36, 20 October 2021
- ...conductor devices. As such, these architectures are often (i) difficult to design, test, or migrate to other technology nodes, due to their analog component, ...e, that it can achieve better area- and energy-efficiency than traditional digital architectures that perform the same operation. These results demonstrate th7 KB (933 words) - 19:29, 21 November 2021
- ...more, PPAC can achieve better area- and energy-efficiency than traditional digital architectures that perform the same operation. This project requires knowledge of digital logic and programming skills in C.7 KB (804 words) - 19:45, 21 November 2021
- * '''[[Design Review]]''' [[Category:Digital]]4 KB (520 words) - 14:52, 24 November 2021
- * '''[[Design Review]]''' [[Category:Digital]]5 KB (564 words) - 16:12, 9 February 2022
- * '''[[Design Review]]''' [[Category:Digital]]5 KB (586 words) - 16:15, 9 February 2022
- [[Category:Digital]] [[Category:Digital Medical Ultrasound Imaging]]7 KB (831 words) - 19:36, 12 January 2023
- In the first part of this project, you will re-design and refactor the existing C-BRED codebase to support additional graph dista [[Category:Digital]]6 KB (839 words) - 14:08, 15 February 2024
- * '''[[Design Review]]''' [[Category:Digital]]4 KB (503 words) - 13:54, 30 May 2022
- guessing accuracy, implement an architecture, and test it on an FPGA. : Familiarity with the basics of digital communication is recommended but not strictly required4 KB (470 words) - 18:16, 27 May 2022
- : Familiarity with the basics of digital communication is recommended but not strictly required * '''[[Design Review]]'''4 KB (492 words) - 10:55, 16 June 2022