Accelerating Applications Relying on Matrix-Vector-Product-Like Operations
With the rise of machine learning, data mining, and 5G wireless communication, matrix-vector products have once again taken the spotlight as one of the most useful operations. Depending on the application, such matrix-vector products are executed in different number formats (for example, GF2 arithmetic for forward-error correction) or numeric representations (mid-rise quantization when working with ADCs). What is more, one could reuse hardware for matrix-vector products to also execute parallel Hamming distance computations, enabling the same hardware substrate to accelerate associative computing.
PPAC (Parallel Processor in Associative Content-Addressable Memory)  is a hardware accelerator that aims at accelerating not only matrix-vector products, but also other, similarly structured operations. PPAC is a processing-in-memory (PIM) architecture which, unlike most existing PIM architectures, is completely digital and implemented using CMOS standard-cells only. These attributes make PPAC very easy to design, implement, and test. We have shown that PPAC achieves an energy-efficiency that is competitive to that of PIM designs that rely on analog computation, and furthermore, PPAC can achieve better area- and energy-efficiency than traditional digital architectures that perform the same operation.
However, our current benchmarks to demonstrate the advantages of PPAC only consider matrix-vector products in the context of machine learning  and equalization for wireless communications . In this project, the student will implement several more applications to be accelerated by PPAC, including (but not limited to) locality sensitive hashing, decoding using the recently proposed GRAND algorithm [3,4], and cryptography algorithms (e.g., AES). In order to have a simpler programming interface and facilitate benchmarking, the student will also integrate PPAC together with a RISC-V processor.
This project requires knowledge of digital logic and programming skills in C.
 O. Castañeda, M. Bobbett, A. Gallyas-Sanhueza, and C. Studer, "PPAC: A Versatile In-Memory Accelerator for Matrix-Vector-Product-Like Operations," IEEE 30th International Conference on Application-specific Systems, Architectures and Processors (ASAP), July 2019
 O. Castañeda, Z. Boynton, S. H. Mirfarshbafan, S. Huang, J. C. Ye, A. Molnar, and C. Studer, "A Resolution-Adaptive 8mm2 9.98Gb/s 39.7pJ/b 32-Antenna All-Digital Spatial Equalizer for mmWave Massive MU-MIMO in 65nm CMOS," IEEE 47th European Solid-State Circuits Conference (ESSCIRC), September 2021
 K. R. Duffy, "Ordered Reliability Bits Guessing Random Additive Noise Decoding," IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), June 2021
 T. Tonnellier, M. Hashemipour, N. Doan, W. J. Gross, and A. Balatsoukas-Stimming, “Towards Practical Near-Maximum-Likelihood Decoding of Error-Correcting Codes: An Overview,” IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), June 2021
- Looking for a 4-semester student (Master semester or bachelor’s thesis); multiple students allowed.
- Contact: Oscar Castañeda
- VLSI I
- VLSI II (recommended)
- 40% Applications
- 20% RTL Design
- 40% Programming