User contributions
From iis-projects
- 09:40, 12 April 2024 diff hist +201 Benchmarking RISC-V-based Accelerator Cards for Inference (multiple SA)
- 09:36, 12 April 2024 diff hist 0 N File:Metis.jpg current
- 09:36, 12 April 2024 diff hist +65 Benchmarking RISC-V-based Accelerator Cards for Inference (multiple SA)
- 09:32, 12 April 2024 diff hist +28 Benchmarking RISC-V-based Accelerator Cards for Inference (multiple SA) →Introduction
- 09:30, 12 April 2024 diff hist 0 N File:E75.png current
- 09:30, 12 April 2024 diff hist +2,959 N Benchmarking RISC-V-based Accelerator Cards for Inference (multiple SA) Created page with "<!-- Benchmarking RISC-V-based Accelerator Cards for Inference (multiple SA) --> Category:Digital Category:High Performance SoCs Category:2023 Category:Semester..."
- 08:42, 12 April 2024 diff hist +7 User:Cykoenig →Cyril Koenig
- 08:41, 12 April 2024 diff hist +70 User:Cykoenig →Cyril Koenig
- 19:46, 11 March 2024 diff hist +530 Benchmarking a RISC-V-based Server on LLMs/Foundation Models (SA or MA)
- 19:18, 11 March 2024 diff hist +105 Benchmarking a RISC-V-based Server on LLMs/Foundation Models (SA or MA)
- 19:12, 11 March 2024 diff hist 0 N File:Pioneer.jpg current
- 15:27, 15 February 2024 diff hist -2 Writing a Hero runtime for EPAC (1-3S/B) current
- 15:57, 13 February 2024 diff hist +7 Building an RTL top level for a Mempool-based Heterogeneous SoC (M/1-3S) current
- 11:40, 13 February 2024 diff hist -1 Building an RTL top level for a Mempool-based Heterogeneous SoC (M/1-3S)
- 11:40, 13 February 2024 diff hist -1 Building an RTL top level for a Mempool-based Heterogeneous SoC (M/1-3S)
- 11:29, 13 February 2024 diff hist 0 Building an RTL top level for a Mempool-based Heterogeneous SoC (M/1-3S)
- 11:07, 13 February 2024 diff hist +186 Building an RTL top level for a Mempool-based Heterogeneous SoC (M/1-3S)
- 12:49, 12 February 2024 diff hist +1 User:Cykoenig
- 12:49, 12 February 2024 diff hist +134 Building an RTL top level for a Mempool-based Heterogeneous SoC (M/1-3S)
- 12:43, 12 February 2024 diff hist +3,026 N Building an RTL top level for a Mempool-based Heterogeneous SoC (M/1-3S) Created page with "<!-- Creating Extending the HERO RISC-V HPC stack to support multiple devices on heterogeneous SoCs (M/1-3S) --> Category:Digital Category:High Performance SoCs Cat..."
- 12:19, 12 February 2024 diff hist +2,986 Writing a Hero runtime for EPAC (1-3S/B)
- 12:19, 12 February 2024 diff hist -72 Extending the HERO RISC-V HPC stack to support multiple devices on heterogeneous SoCs (M/1-3S)
- 12:18, 12 February 2024 diff hist +71 Extending the HERO RISC-V HPC stack to support multiple devices on heterogeneous SoCs (M/1-3S) →Project
- 12:07, 12 February 2024 diff hist 0 File:Epac backend.png Cykoenig uploaded a new version of File:Epac backend.png current
- 12:05, 12 February 2024 diff hist 0 N File:Epac backend.png
- 20:01, 2 February 2024 diff hist +1,163 Extending the HERO RISC-V HPC stack to support multiple devices on heterogeneous SoCs (M/1-3S)
- 19:51, 2 February 2024 diff hist 0 N File:Hero heterogeneous2.png current
- 19:48, 2 February 2024 diff hist 0 File:Hero heterogeneous.png Cykoenig uploaded a new version of File:Hero heterogeneous.png current
- 19:47, 2 February 2024 diff hist 0 N File:Hero heterogeneous.png
- 19:36, 2 February 2024 diff hist 0 N File:Hero carfield.png current
- 19:36, 2 February 2024 diff hist +255 Extending the HERO RISC-V HPC stack to support multiple devices on heterogeneous SoCs (M/1-3S) →Project
- 19:32, 2 February 2024 diff hist +1,256 Extending the HERO RISC-V HPC stack to support multiple devices on heterogeneous SoCs (M/1-3S) →Introduction
- 11:16, 25 January 2024 diff hist -56 Writing a Hero runtime for EPAC (1-3S/B)
- 11:15, 25 January 2024 diff hist +697 N Extending the HERO RISC-V HPC stack to support multiple devices on heterogeneous SoCs (M/1-3S) Created page with "<!-- Creating Extending the HERO RISC-V HPC stack to support multiple devices on heterogeneous SoCs (M/1-3S) --> Category:Digital Category:High Performance SoCs Cat..."
- 11:10, 25 January 2024 diff hist 0 User:Cykoenig
- 11:10, 25 January 2024 diff hist +23 Writing a Hero runtime for EPAC (1-3S/B)
- 11:09, 25 January 2024 diff hist +3 Writing a Hero runtime for EPAC (1-3S/B) →Status: Available
- 11:08, 25 January 2024 diff hist +666 N Writing a Hero runtime for EPAC (1-3S/B) Created page with "<!-- Creating Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B) --> Category:Digital Category:High Performance SoCs Category:H..."
- 11:01, 25 January 2024 diff hist +1 User:Cykoenig →Research
- 11:01, 25 January 2024 diff hist +64 User:Cykoenig →Cyril Koenig
- 10:54, 25 January 2024 diff hist +679 High Performance SoCs Ordered users by alphabetical order and added Cykoenig current
- 10:49, 25 January 2024 diff hist +22 A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B) current
- 10:47, 25 January 2024 diff hist +22 Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S) current
- 10:47, 25 January 2024 diff hist +666 User:Cykoenig
- 10:43, 25 January 2024 diff hist 0 N File:Cykoenig face pulp team.png current
- 12:07, 20 December 2022 diff hist 0 A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B) →Project Supervisors
- 12:07, 20 December 2022 diff hist +95 A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B) →Status: Available
- 18:34, 7 November 2022 diff hist +135 User:Cykoenig
- 18:32, 7 November 2022 diff hist 0 N User:Cykoenig Created blank page
- 18:32, 7 November 2022 diff hist +94 A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B) →Project Supervisors