Difference between revisions of "Advanced Physical Design: Reinforcement Learning for Macro Placement and Mix-Placer (B/1-2S)"
From iis-projects
Latest revision as of 10:50, 3 November 2023
Contents
Overview
Status: Available
- Type: Semester Thesis or Bachelor Thesis
- Professor: Prof. Dr. L. Benini
- Supervisors:
Introduction
In June 2021, the Google Brain and Chip Implementation and Infrastructure (CI2) teams introduced an innovative reinforcement learning (RL) methodology for macro placement, as documented in a Nature publication. The authors highlighted the efficiency and effectiveness of their approach, stating, “In under six hours, our method automatically generates chip floorplans that are superior or comparable to those produced by humans across all crucial metrics, including power consumption, performance, and chip area.” The reported results showcased a marked superiority over academic placers and simulated annealing techniques.
For the MemPool/TeraPool project, managing the floorplan becomes a formidable challenge, especially given the presence of up to 4096 memory bank macros. A well-thought-out automatic floorplan flow is crucial, as it not only shortens the design cycle but also significantly enhances the area utilization and overall performance of the design. Achieving an optimal floorplan necessitates meticulous optimization of the interconnection paths between the processing elements and memory banks, ensuring efficient data flow and reduced latency.
Building upon this groundbreaking work, our project aims to explore advanced EDA flows with these open-sourced reinforcement-learning-powered(RL) floorplan(FP) tools specifically for macro placement. We also intend to delve into Mix-Placer, a technique that involves the strategic placement of macros and standard cells. By conducting a comprehensive comparison with floorplans created by human experts, our goal is to significantly enhance the physical design’s Power, Performance, and Area (PPA).
Project
This thesis aims to go deeper into the backend design and optimization of Floorplans. The specific areas of exploration can include:
Open-Sourced RL FP tools: students are expected to delve into various open-source methodologies to determine the most suitable approach for our many-core based HPC cluster, encompassing MemPool and TeraPool. Here’s a comprehensive guide to assist in evaluating and comparing these methods:CT/ RePlAce/ AutoDMP/ CMP and Simulated Annealing.
Detailed Physical Design PPA analysis: Utilizing the aforementioned RL FP methods, this section delves into a comprehensive comparison with the floorplans crafted by human experts. We aim to quantify the performance enhancements achievable, scrutinize the distribution of routing resources, and ascertain the extent of die area reduction. Through this analysis, we will illuminate the design intricacies and highlight the inherent trade-offs involved.
Character
- 30% Literature Research
- 50% Advanced Physical Design EDA Flow Exploration
- 10% Simulation and Evaluation
- 10% Documentation & Report
Prerequisites
- The student should have attended the VLSI 2 course.
- Previous backend experience (i.e. a chip tapeout) is advantageous but not required
- Some familiarity with the concept of Manycore architecture is recommended
