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Difference between revisions of "Baseband Processor Development for 4G IoT"

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[[File:4G_soc.png|thumb|4G modem SoC with RF, DBB, and L2/L3.]]
 
[[File:2G_testbed.jpg|thumb|2G Testbed setup with L2/L3 processing on ZedBoard (top), double RF on evalEDGE v1.0 (middle), and baseband on ML605 (bottom).]]
 
[[File:2G_testbed.jpg|thumb|2G Testbed setup with L2/L3 processing on ZedBoard (top), double RF on evalEDGE v1.0 (middle), and baseband on ML605 (bottom).]]
  
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Various estimates predict 20 to 30 billion embedded devices connected to the Internet in 2020 in what’s called the the Internet of things (IoT). To realize this vision, cellular standards are released to meet the requirements regarding low-power and low-cost of IoT components, especially on the client side. In the latest release of the LTE standard, a new user-equipment category (Cat-0) for Machine to Machine (M2M) communications and the Internet of things (IoT) was introduced [1]. In order to develop signal processing algorithms for the fast evolving LTE landscape a fast prototyping platform is indispensable.
 
Various estimates predict 20 to 30 billion embedded devices connected to the Internet in 2020 in what’s called the the Internet of things (IoT). To realize this vision, cellular standards are released to meet the requirements regarding low-power and low-cost of IoT components, especially on the client side. In the latest release of the LTE standard, a new user-equipment category (Cat-0) for Machine to Machine (M2M) communications and the Internet of things (IoT) was introduced [1]. In order to develop signal processing algorithms for the fast evolving LTE landscape a fast prototyping platform is indispensable.
  
The goal of this project is to design an FPGA-based testbed for 4G/LTE mobile communication. It shall consist of a commercial FPGA board (ML605, see [2]) and a custom RF transceiver extension card. The extension card is currently under development and will have similar features as [[evalEDGE]] but it will be LTE capable using RF solutions from [3]. The FPGA on the ML605 shall be used for RF controlling and baseband processing. In addition, the results from [[Baseband Meets CPU]] can be used to incorporate higher layer processing using a [[PULP]] CPU on the FPGA, as well. Once the testbed is running the baseband processing can be enhanced and software to run on the PULP can be written and immediately tested.
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A 4G cellular modem consists of an RF front-end, hardwired Digital Baseband (DBB) processing, and L2/L3 processing on a CPU. It is advantageous to use an FPGA as base. This way improvements to DBB and CPU architecture can be updated immediately to the prototype and software running on the CPU can take advantage of those improvements.
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The goal of this project is to design an FPGA-based prototyping platform for 4G/LTE mobile communication. It shall consist of a commercial FPGA board (ML605, see [2]) and a custom RF transceiver extension card. The extension card is currently under development and will have similar features as [[evalEDGE]] but it will be LTE capable using RF solutions from [3]. The FPGA on the ML605 shall be used for RF controlling and baseband processing. In addition, the results from [[Baseband Meets CPU]] can be used to incorporate higher layer processing using a [[PULP]] CPU on the FPGA, as well. Once the testbed is running the baseband processing can be enhanced and software to run on the PULP can be written and immediately tested.
  
 
===Status: Available ===
 
===Status: Available ===
 
: Looking for 1 Master student
 
: Looking for 1 Master student
: Supervision: [[User:Weberbe|Benjamin Weber]], [[User:Kroell|Harald Kröll]]
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: Supervision: [[User:Weberbe|Benjamin Weber]], [[User:Vogelpi|Pirmin Vogel]]
  
 
===Character===
 
===Character===
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===Professor===
 
===Professor===
 
[http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang]
 
[http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang]
 +
or
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[http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini]
  
 
==References==  
 
==References==  
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[[Category:Telecommunications]]
 
[[Category:Telecommunications]]
 
[[Category:Weberbe]]
 
[[Category:Weberbe]]
[[Category:Kroell]]
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[[Category:Vogelpi]]

Revision as of 13:15, 28 May 2015

4G modem SoC with RF, DBB, and L2/L3.
2G Testbed setup with L2/L3 processing on ZedBoard (top), double RF on evalEDGE v1.0 (middle), and baseband on ML605 (bottom).

Short Description

Various estimates predict 20 to 30 billion embedded devices connected to the Internet in 2020 in what’s called the the Internet of things (IoT). To realize this vision, cellular standards are released to meet the requirements regarding low-power and low-cost of IoT components, especially on the client side. In the latest release of the LTE standard, a new user-equipment category (Cat-0) for Machine to Machine (M2M) communications and the Internet of things (IoT) was introduced [1]. In order to develop signal processing algorithms for the fast evolving LTE landscape a fast prototyping platform is indispensable.

A 4G cellular modem consists of an RF front-end, hardwired Digital Baseband (DBB) processing, and L2/L3 processing on a CPU. It is advantageous to use an FPGA as base. This way improvements to DBB and CPU architecture can be updated immediately to the prototype and software running on the CPU can take advantage of those improvements.

The goal of this project is to design an FPGA-based prototyping platform for 4G/LTE mobile communication. It shall consist of a commercial FPGA board (ML605, see [2]) and a custom RF transceiver extension card. The extension card is currently under development and will have similar features as evalEDGE but it will be LTE capable using RF solutions from [3]. The FPGA on the ML605 shall be used for RF controlling and baseband processing. In addition, the results from Baseband Meets CPU can be used to incorporate higher layer processing using a PULP CPU on the FPGA, as well. Once the testbed is running the baseband processing can be enhanced and software to run on the PULP can be written and immediately tested.

Status: Available

Looking for 1 Master student
Supervision: Benjamin Weber, Pirmin Vogel

Character

10% Theory
60% System/FPGA Design
30% Software

Prerequisites

VLSI I
Matlab, VHDL, C

Professor

Qiuting Huang or Luca Benini

References

[1] Redefining LTE for IoT. http://www.nextgcom.co.uk/wordpress/wp-content/uploads/2014/09/ARM-NextG-LTE-Cat0-White-Paper-Final.pdf, May 2015.

[2] XILINX. Virtex-6 FPGA ML605 Evaluation Kit. http://www.xilinx.com/ml605, May 2015.

[3] Advanced Circuit Pursuit, ACP AG. http://www.newacp.ch/, May 2015.