Revision as of 20:51, 11 October 2022

Overview

Status: Available

• Type: Semester or Master Thesis
• Professor: Prof. Dr. L. Benini
• Supervisors:
  • Luca Colagrande: colluca@iis.ee.ethz.ch

Introduction

Occamy is a massively-parallel multiprocessor system-on-chip (MPSoC) designed for energy-efficient high-performance computing applications. It couples an application-class out-of-order CVA6 core [1,2] which can boot Linux to a many-core accelerator comprising 216 energy-efficient Snitch cores [3,4].

This heterogeneous platform guarantees high single-thread performance for sequential code executing on CVA6, while parallel code regions can be offloaded to the accelerator to take advantage of its higher energy efficiency and peak performance. The heterogeneous programming model described opens up many interesting questions for exploration, such as:

• When is it convenient to offload a computation on the accelerator?
• What is the optimal number of accelerator cores to select for offload?

Given the rising popularity of heterogeneous MPSoCs [5,6], being able to comfortably answer these questions should be considered a valuable skill set.

In addition to providing a Snitch’s floating-point subsystem is of particular interest as it integrates several ISA extensions: stream semantic registers (SSRs) [2] and the floating-point repetition (FREP) instruction extension .

Project

Character

Prerequisites

References

[1] https://github.com/openhwgroup/cva6
[2] https://arxiv.org/pdf/1904.05442.pdf
[3] https://github.com/pulp-platform/snitch
[4] https://arxiv.org/pdf/2002.10143.pdf
[5] https://en.wikichip.org/wiki/nvidia/tegra/xavier
[6] https://en.wikipedia.org/wiki/ARM_big.LITTLE