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CPS Software-Configurable State-Machine

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Short Description

More and more sensors devices are placed in buildings, industrial plants, the environment - even in every day products like clothing or food products. Most of these system aim for continuous monitoring of environmental parameters and periodically report their data over a wireless link. Some of these system even include an actuation system, which reacts depending on the captured data. If many of such components are connected and operate and act collaboratively it is called a 'cyper-physical system' (CPS).

For a large subset of these components energy consumption is an issue, since changing batteries often is uneconomical and unpractical. Moreover, many of these system have a very low duty cycle: In the majority of time they are idling. Periodically, they turn on and perform a very simple task - like capturing a sample - and even less often they handle more complex tasks, like compressing data and sending them over a wireless link.

Today, low-power microcontrollers are used as the core unit of such a system to handle both scheduling and the processing of the tasks. If no tasks have to be handled, the microcontroller is usually in deep sleep mode and a small counter is expiring for periodical wake-ups. If a task has to be performed, the microcontroller must boot up - no matter how simple the task to perform is - perform the task and go back to sleep. This transition can burn a lot of power and reduce battery life.

In this work, we want to explore the usage of a software-configurable hardware state machine, which can be used for scheduling and executing very simple tasks at a very low power budget, without having to power up the processor. Together with a low power timer, the state-machine forms what we call the CPS scheduling subsystem.


To save power, this unit will not be a conventional fully synchronously clocked design: the configurable state-machine will be clocked on an event basis only.

The goal of this Semester/Master Thesis is to work out a first architecture of the hardware-configurable state-machine and - in the case of a Master Thesis - a first silicon implementation.

Status: Available

Semester/Master Thesis
Supervision: Pascal Alexander Hager (IIS)


Luca Benini


60% Theory, Algorithms and Simulation
40% VHDL


Knowledge of matlab and/or C/C++ VHDL


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