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Compressed Sensing vs JPEG

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Short Description

Compressed Sensing (CS) is a signal processing scheme that aims at combining signal acquisition and data compression in one single step and close to the sensor. CS can be implemented very efficiently in digital logic, and the encoding (or compression) step can be performed with very little hardware (and power) effort. Instead, the reconstruction (or decompression) step requires fairly sophisticated algorithms. Understood as data compression/decompression strategy, CS is a highly asymmetric CODEC making its application in low-power wireless telemetry applications attractive (e.g., smart watches or wireless low-power webcams).

In this project, we are interested in applying CS to low resolution image compression and compare it to well-established strategies, such as JPEG for example. JPEG is widely used in practice, and is based on transform coding using the DCT (Discrete Cosine Transform), variable quantization and entropy encoding to obtain a more or less lossy compression of raw image data. The computational complexity of both the encoding of raw data and decoding of the image from the compressed data is approximately equal. The goal of this project is to see whether the assymmetry of CS can be leveraged to reduce the hardware complexity and power consumption of the encoding stage, and how the compression performance and image quality compare to JPEG.

This project may be extended to include the design of a digital ASIC (Application Specific Integrated Circuit) or the implementation in FPGA (Field-Programmable Gate Array).

These are the topics you will deal with:

- Integrated hardware design
- The basics of Compressed Sensing
- Image compression, in general, and JPEG, in particular.
- The basics of DCT (Discrete Cosine Transform) and FFT (Fast Fourier Transform)
- The basics of entropy encoding, Huffman encoding in particular

Status: Available

Looking for 1 Master student or 2 semester-project students
Supervision: David Bellasi


20% Theory
60% Matlab Simulation
20% VLSI or FPGA design


Matlab, VHDL


Luca Benini