Designing a Fault-Tolerant On-Chip Interconnect (1-2S/M)
From iis-projects
Overview
Status: Available
- Type: Semester Thesis
- Professor: Prof. Dr. L. Benini
- Supervisors:
Introduction
In the PULP group, we have started developing reliable hardware designed for use in space, where high levels of radiation have a significant impact on the correctness of executions.
While many processing elements and memory elements have been investigated and protected, the fabric holding everything together, the communication interconnect, has not been thoroughly analyzed yet.
Project
Aim of this project is to develop one (or more) protection schemes to detect and recover from runtime faults or Single Event Upsets (SEUs) within an SoC interconnect.
Character
- 10% Literature Research
- 50% Architecture Design
- 20% Performance and Fault Tolerance Evaluation
- 20% Documentation & Report
Prerequisites
- Experience with digital design in SystemVerilog as taught in VLSI I
