Difference between revisions of "Designing a Scalable Miniature I/O DMA (1-2B/1-3S/M)"
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Latest revision as of 14:24, 27 February 2024
Contents
Overview
Status: In Progress
- Type: Bachelor / Semester / Master Thesis
- Professor: Prof. Dr. L. Benini
- Supervisors:
Introduction
At IIS we are developing an architectural family of lightweight yet high-performance data movement engines (iDMA)[1].
Furthermore, our PULPissimo systems use a different DMA architecture (uDMA [2]), specifically designed to interact with SoC peripherals.
Project
The goal of this project is to replace the internal data movement component within the uDMA with the iDMA, simplifying the code base within the design.
Depending on the progress, this project could result in a Tapeout.
Character
- 40% RTL Design and Verification
- 20% Software / Driver / HAL writing (C)
- 40% Evaluation
Prerequisites
- Experience with digital design in SystemVerilog as taught in VLSI I
