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Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B)

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Status: Available


Transposing matrices is an important operation used in countless applications from scientific computing to machine learning workloads.

At IIS, we are actively developing a DMA engine to accelerate data movement in various of our platforms. We would now create a transposition unit that transposes matrices while they are copied throughout the system. The accelerator should work of full-precision integer and floating point formats for general purpose scientific computing as well as narrow 4bit / 2bit (and even 1bit?) typed for ML interference.


In this project, you develop, implement, and evaluate a flexible transposition unit able to work on various data widths.


  • 40% Design and implementation of the unit
  • 30% Verification
  • 30% Evaluation


  • Interest in memory systems
  • Experience with digital design in SystemVerilog as taught in VLSI I
  • Preferred: Knowledge of AXI4