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Difference between revisions of "Energy Efficient Serial Link"

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===Status: Available===
 
===Status: Available===
 
:Looking for master or semester thesis students
 
:Looking for master or semester thesis students
:Supervisor: [[:User:sarjmandpour | Sina Arjmandpour]]
+
:Supervisor:  
 +
**[[:User:sarjmandpour | Sina Arjmandpour]]: [mailto:sarjmandpour@iis.ee.ethz.ch sarjmandpour@iis.ee.ethz.ch]
 +
** [[:User:Fischeti | Tim Fischer]]: [mailto:fischeti@iis.ee.ethz.ch fischeti@iis.ee.ethz.ch]
  
 
===Prerequisites===
 
===Prerequisites===
* VLSI  
+
* Experience with System Verilog, VLSI 1
 +
* Experience with physical implementation, VLSI 2
 +
 
  
 
===Character===
 
===Character===
* 20% Literature review
+
* 20% System Integration
* 20% Theory
+
* 20% Verification
* 60% Programming
+
* 30% Low-level software and drivers
 +
* 30% Backend implementation
  
 
===Professor===
 
===Professor===
Prof. Taekwang Jang <[mailto:tjang@ethz.ch tjang@ethz.ch]>
+
*Prof. Dr. Luca Benini
 +
*Prof. Dr. Taekwang Jang
  
 
=== Reference===
 
=== Reference===

Revision as of 13:06, 13 February 2023

Description

Status: Available

Looking for master or semester thesis students
Supervisor:

Prerequisites

  • Experience with System Verilog, VLSI 1
  • Experience with physical implementation, VLSI 2


Character

  • 20% System Integration
  • 20% Verification
  • 30% Low-level software and drivers
  • 30% Backend implementation

Professor

  • Prof. Dr. Luca Benini
  • Prof. Dr. Taekwang Jang

Reference

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Practical Details