Difference between revisions of "Energy Efficient Serial Link"
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===Prerequisites=== | ===Prerequisites=== | ||
| − | * Experience with System Verilog, VLSI 1 | + | * Experience with System Verilog/ Verilog, VLSI 1 |
* Experience with physical implementation, VLSI 2 | * Experience with physical implementation, VLSI 2 | ||
| − | |||
===Character=== | ===Character=== | ||
Revision as of 13:06, 13 February 2023
Contents
Description
Status: Available
- Looking for master or semester thesis students
- Supervisor:
Prerequisites
- Experience with System Verilog/ Verilog, VLSI 1
- Experience with physical implementation, VLSI 2
Character
- 20% System Integration
- 20% Verification
- 30% Low-level software and drivers
- 30% Backend implementation
Professor
- Prof. Dr. Luca Benini
- Prof. Dr. Taekwang Jang
