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Extend the RI5CY core with priviledge extensions

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The RI5CY core is one of the most famous open-source microprocessors that implements the RISC-V ISA. It has been designed for small embedded system platforms mostly used in IoT devices. Its ISA implements RISC-V's RV32IMFC plus custom instructions that have been designed to efficiently deal with digital-signal-processing applications typical for near-sensor systems.

Recently RI5CY as well as the PULP platforms have been chosen and/or evaluated by big companies like Google, IBM, micron, NXP, Dolphin Integration, GreenWaves Technology etc.

In particular, Google has evaluated the RI5CY core for being integrated in the Pixel Visual Core and they showed how the verification has been done for its evaluation:

To be cost- and area efficient, RI5CY only implements a subset of the priviledged ISA. The subset however allows low-complex operating systems such as FreeRTOS to run on PULP platforms. However, the ever increase demanding of security on embedded systems make it necessary to run more complex operating systems. Those typically require more than one priviledge level.

For instance, tiny operating sytems with minimalistic security need at least machine (M) and user (U) mode to be implemented in the core, whereas more complex OS like Linux require at least 3 levels, M, U and supervisor mode (S). MMU or MPU are also needed by these systems to filter bad memory requests according to the current priviledge level.

Project description

Furthermore, the core has to be able to interact with different priviledged interrupt requests. The student willing to join the PULP team and work with our core is required to:

1. Take confidence with the current core architecture, understading the pipeline of the core and its functionality. This is achieved by studying its code, fix tiny problems to get confidence with our git enviroment, build a testbench for the core to test the IP isolated by the rest of the system. (~3-4 weeks)

2. Change the pipeline of the core to support the U-priviledge mode. Parts of it are already in place. The student will focus especially on the memory exeptions and in the design of an MMU. The student is required to extend the testbench to emulated the security context, different interrupts requests etc. The verification will be one of the most imporant parts of the thesis (~6-9 weeks)

3. Extend the PULPissimo platform and extend the current interrupt controller to support multilevel (2 levels) interrupts requests. This part may slightly change and has to be discussed during the thesis. (~3 weeks)

4. Evaluate the speed, area and power overhead of the PULPissimo platform with security support compared to the version without the priviledge support in 65nm. (~3 weeks) If the student is fast and he wants to have extra fun, an FPGA implementation of the PULPissimo platform can be done to show small demo and the functionality of work . This thesis can also be taken by 2 students for a semester thesis.

If the outcome of the thesis is valid and well performed, the student will have the possibility to attend and/or present his/her work to the RISC-V Workshop!

Required Skills

To work on this project, you will need:

  • to have worked in the past with at least one RTL language (SystemVerilog or Verilog or VHDL) - having followed the VLSI1 / VLSI2 courses is recommended
  • to have prior knowedge of hardware design and computer architecture - having followed the Advances System-on-Chip Design course is recommended
  • to be strongly motivated for a difficult but super-cool project
  • to be able to work in a team

Status: Available

Supervision: Pasquale Davide Schiavone


Luca Benini

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Supervisors: Davide Schiavone