Information for "Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B)"
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Basic information
| Display title | Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B) |
| Default sort key | Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B) |
| Page length (in bytes) | 2,710 |
| Page ID | 1748 |
| Page content language | English (en) |
| Page content model | wikitext |
| Indexing by robots | Allowed |
| Number of redirects to this page | 0 |
| Counted as a content page | Yes |
Page protection
| Edit | Allow all users (infinite) |
| Move | Allow all users (infinite) |
Edit history
| Page creator | Tbenz (talk | contribs) |
| Date of page creation | 18:20, 15 August 2022 |
| Latest editor | Tbenz (talk | contribs) |
| Date of latest edit | 09:38, 3 November 2023 |
| Total number of edits | 2 |
| Total number of distinct authors | 1 |
| Recent number of edits (within past 90 days) | 0 |
| Recent number of distinct authors | 0 |
